working?

1 files changed, 48 insertions, 22 deletions

diff --git a/lab3/lab.vhd b/lab3/lab.vhd
index f50bfac..d699e49 100755
--- a/lab3/lab.vhd
+++ b/lab3/lab.vhd
@@ -30,7 +30,7 @@ architecture Behavioral of lab is
 
     signal bit_cycle : UNSIGNED(11 downto 0) := X"000";  -- fits at least 868
     signal bits_received : UNSIGNED(3 downto 0) := X"0";
-    signal receiving: std_logic; -- currently receiving a byte
+    signal receiving : std_logic; -- currently receiving a byte
 
 begin
     -- *****************************
@@ -71,12 +71,13 @@ begin
             elsif receiving = '1' then
                 -- have we waited for an uart cycle?
                 if bit_cycle = X"364" then
-                    -- yes. read uart data
-                    bits_received <= bits_received + 1;
-                    if bits_received = "10" then
+                    -- yes. read uart bit
+                    if bits_received = X"9" then
                         receiving <= '0';
+                        bits_received <= X"0";
                     else
                         bit_cycle <= X"000";
+                        bits_received <= bits_received + 1;
                     end if;
                 else
                     bit_cycle <= bit_cycle + 1;
@@ -102,7 +103,13 @@ begin
             else
                 if (receiving = '1') and (bit_cycle = X"364") then
                     sp <= '1';
-                    lp <= '1' if bits_received = "10" else '0';
+                else
+                    sp <= '0';
+                end if;
+                if (sp = '1') and (receiving = '0') then
+                    lp <= '1'
+                else
+                    lp <= '0';
                 end if;
             end if;
         end if;
@@ -116,14 +123,24 @@ begin
     --
     -- De 10 bitarna i varje siffra skiftas in i skiftregistret.
 
-    -- process(clk) begin
-    --     if rising_edge(clk) then
-    --         if rst='1' then
-    --         elsif _ then
-    --         else
-    --         end if;
-    --     end if;
-    -- end process;
+    process(clk) begin
+        if rising_edge(clk) then
+            if rst = '1' then
+                sreg <= B"0_000_000_0";
+            elsif sp = '1' then
+                sreg(0) <= sreg(1);
+                sreg(1) <= sreg(2);
+                sreg(2) <= sreg(3);
+                sreg(3) <= sreg(4);
+                sreg(4) <= sreg(5);
+                sreg(5) <= sreg(6);
+                sreg(6) <= sreg(7);
+                sreg(7) <= sreg(8);
+                sreg(8) <= sreg(9);
+                sreg(9) <= rx2;
+            end if;
+        end if;
+    end process;
 
 
     -- *****************************
@@ -134,6 +151,7 @@ begin
     process(clk) begin
         if rising_edge(clk) then
             if rst='1' then
+                pos <= "00";
             elsif lp = '1' then
                 if pos = "11" then
                     pos <= "00";
@@ -153,15 +171,23 @@ begin
     --
     -- ... för 4 siffror. Laddas av laddpulsen, samtidigt räknas räknaren upp.
 
-
-    -- process(clk) begin
-    --     if rising_edge(clk) then
-    --         if rst='1' then
-    --         elsif _ then
-    --         else
-    --         end if;
-    --     end if;
-    -- end process;
+    process(clk) begin
+        if rising_edge(clk) then
+            if rst='1' then
+                tal <= X"0000";
+            elsif lp = '1' then
+                if pos = "00" then
+                    tal(3 downto 0) <= unsigned(sreg(8 downto 1));
+                elsif pos = "01" then
+                    tal(7 downto 4) <= unsigned(sreg(8 downto 1));
+                elsif pos = "10" then
+                    tal(11 downto 8) <= unsigned(sreg(8 downto 1));
+                else
+                    tal(15 downto 12) <= unsigned(sreg(8 downto 1));
+                end if;
+            end if;
+        end if;
+    end process;
 
 
     -- *****************************