more align

2 files changed, 37 insertions, 37 deletions

diff --git a/lab4/VGA_MOTOR/VGA_lab.vhd b/lab4/VGA_MOTOR/VGA_lab.vhd
index f96206a..317ff84 100644
--- a/lab4/VGA_MOTOR/VGA_lab.vhd
+++ b/lab4/VGA_MOTOR/VGA_lab.vhd
@@ -13,13 +13,13 @@ use IEEE.NUMERIC_STD.ALL;               -- IEEE library for the unsigned type
 
 -- entity
 entity VGA_lab is
-  port ( clk	                : in std_logic;                         -- system clock
-	 rst                    : in std_logic;                         -- reset
-	 Hsync	                : out std_logic;                        -- horizontal sync
-	 Vsync	                : out std_logic;                        -- vertical sync
-	 vgaRed	                : out	std_logic_vector(2 downto 0);   -- VGA red
-	 vgaGreen               : out std_logic_vector(2 downto 0);     -- VGA green
-	 vgaBlue	        : out std_logic_vector(2 downto 1));     -- VGA blue
+  port ( clk                    : in std_logic;                              -- system clock
+         rst                    : in std_logic;                              -- reset
+         Hsync                  : out std_logic;                             -- horizontal sync
+         Vsync                  : out std_logic;                             -- vertical sync
+         vgaRed                 : out        std_logic_vector(2 downto 0);   -- VGA red
+         vgaGreen               : out std_logic_vector(2 downto 0);          -- VGA green
+         vgaBlue                : out std_logic_vector(2 downto 1);          -- VGA blue
 end VGA_lab;
 
 
@@ -28,41 +28,41 @@ architecture Behavioral of VGA_lab is
 
   -- picture memory component
   component PICT_MEM
-    port ( clk			: in std_logic;                         -- system clock
-	 -- port 1
-           we1		        : in std_logic;                         -- write enable
-           data_in1	        : in std_logic_vector(7 downto 0);      -- data in
-           data_out1	        : out std_logic_vector(7 downto 0);     -- data out
-           addr1	        : in unsigned(10 downto 0);             -- address
-	 -- port 2
-           we2			: in std_logic;                         -- write enable
-           data_in2	        : in std_logic_vector(7 downto 0);      -- data in
-           data_out2	        : out std_logic_vector(7 downto 0);     -- data out
-           addr2		: in unsigned(10 downto 0));            -- address
+    port ( clk                  : in std_logic;                         -- system clock
+         -- port 1
+           we1                  : in std_logic;                         -- write enable
+           data_in1             : in std_logic_vector(7 downto 0);      -- data in
+           data_out1            : out std_logic_vector(7 downto 0);     -- data out
+           addr1                : in unsigned(10 downto 0);             -- address
+         -- port 2
+           we2                  : in std_logic;                         -- write enable
+           data_in2             : in std_logic_vector(7 downto 0);      -- data in
+           data_out2            : out std_logic_vector(7 downto 0);     -- data out
+           addr2                : in unsigned(10 downto 0));            -- address
   end component;
-	
+        
   -- VGA motor component
   component VGA_MOTOR
-    port ( clk			: in std_logic;                         -- system clock
-           rst			: in std_logic;                         -- reset
-           data			: in std_logic_vector(7 downto 0);      -- data
-           addr			: out unsigned(10 downto 0);            -- address
-           vgaRed		: out std_logic_vector(2 downto 0);     -- VGA red
-           vgaGreen	        : out std_logic_vector(2 downto 0);     -- VGA green
-           vgaBlue		: out std_logic_vector(2 downto 1);     -- VGA blue
-           Hsync		: out std_logic;                        -- horizontal sync
-           Vsync		: out std_logic);                       -- vertical sync
+    port ( clk                  : in std_logic;                         -- system clock
+           rst                  : in std_logic;                         -- reset
+           data                 : in std_logic_vector(7 downto 0);      -- data
+           addr                 : out unsigned(10 downto 0);            -- address
+           vgaRed               : out std_logic_vector(2 downto 0);     -- VGA red
+           vgaGreen             : out std_logic_vector(2 downto 0);     -- VGA green
+           vgaBlue              : out std_logic_vector(2 downto 1);     -- VGA blue
+           Hsync                : out std_logic;                        -- horizontal sync
+           Vsync                : out std_logic);                       -- vertical sync
   end component;
-	
+
   -- intermediate signals between PICT_MEM and VGA_MOTOR
-  signal	data_out2_s     : std_logic_vector(7 downto 0);         -- data
-  signal	addr2_s		: unsigned(10 downto 0);                -- address
-	
+  signal  data_out2_s           : std_logic_vector(7 downto 0);         -- data
+  signal  addr2_s               : unsigned(10 downto 0);                -- address
+
 begin
 
   -- picture memory component connection
   U1 : PICT_MEM port map(clk=>clk, we1=>'0', data_in1=>"00000000", addr1=>"00000000000", we2=>'0', data_in2=>"00000000", data_out2=>data_out2_s, addr2=>addr2_s);
-	
+
   -- VGA motor component connection
   U2 : VGA_MOTOR port map(clk=>clk, rst=>rst, data=>data_out2_s, addr=>addr2_s, vgaRed=>vgaRed, vgaGreen=>vgaGreen, vgaBlue=>vgaBlue, Hsync=>Hsync, Vsync=>Vsync);
 
diff --git a/lab4/VGA_lab.vhd b/lab4/VGA_lab.vhd
index 8d3c612..06e0c0c 100644
--- a/lab4/VGA_lab.vhd
+++ b/lab4/VGA_lab.vhd
@@ -53,7 +53,7 @@ architecture Behavioral of VGA_lab is
            data_out2            : out std_logic_vector(7 downto 0);     -- data out
            addr2                : in unsigned(10 downto 0));            -- address
   end component;
-        
+
   -- VGA motor component
   component VGA_MOTOR
     port ( clk                  : in std_logic;                         -- system clock
@@ -66,16 +66,16 @@ architecture Behavioral of VGA_lab is
            Hsync                : out std_logic;                        -- horizontal sync
            Vsync                : out std_logic);                       -- vertical sync
   end component;
-        
+
   -- intermediate signals between KBD_ENC and PICT_MEM
   signal  data_s                : std_logic_vector(7 downto 0);         -- data
   signal  addr_s                : unsigned(10 downto 0);                -- address
   signal  we_s                  : std_logic;                            -- write enable
-        
+
   -- intermediate signals between PICT_MEM and VGA_MOTOR
   signal  data_out2_s           : std_logic_vector(7 downto 0);         -- data
   signal  addr2_s               : unsigned(10 downto 0);                -- address
-        
+
 begin
 
   -- keyboard encoder component connection