add rest of lab3

17 files changed, 1311 insertions, 0 deletions

diff --git a/lab3/Makefile b/lab3/Makefile
new file mode 100755
index 0000000..23d2668
--- /dev/null
+++ b/lab3/Makefile
@@ -0,0 +1,68 @@
+# Makefile for hardware implementation on Xilinx FPGAs and ASICs
+# Author: Andreas Ehliar <ehliar@isy.liu.se>
+# 
+# T is the testbench file for this project
+# S is the synthesizable sources for this project
+# U is the UCF file
+# PART is the part
+
+# Important makefile targets:
+# make lab.sim		GUI simulation
+# make lab.simc		batch simulation
+# make lab.synth	Synthesize
+# make lab.route	Route the design
+# make lab.bitgen	Generate bit file
+# make lab.timing	Generate timing report
+# make lab.clean	Use whenever you change settings in the Makefile!
+# make lab.prog		Downloads the bitfile to the FPGA. NOTE: Does not
+#                       rebuild bitfile if source files have changed!
+# make clean            Removes all generated files for all projects. Also
+#                       backup files (*~) are removed.
+# 
+# VIKTIG NOTERING: 	Om du ändrar vilka filer som finns med i projektet så måste du köra
+#                  	make lab.clean
+#
+# Syntesrapporten ligger i lab-synthdir/xst/synth/design.syr
+# Maprapporten (bra att kolla i för arearapportens skull) ligger i lab-synthdir/layoutdefault/design_map.mrp
+# Timingrapporten (skapas av make lab.timing) ligger i lab-synthdir/layoutdefault/design.trw
+
+# (Or proj2.simc, proj2.sim, etc, depending on the name of the
+# project)
+
+XILINX_INIT = source /opt/xilinx_ise/14.7/settings64.sh;
+PART=xc6slx16-3-csg324
+
+
+lab.%: S=lab.vhd leddriver.vhd
+lab.%: T=lab_tb.vhd
+lab.%: U=lab.ucf
+
+
+# Det här är ett exempel på hur man kan skriva en testbänk som är
+# relevant, även om man kör en simulering i batchläge (make batchlab.simc)
+batchlab.%: S=lab.vhd leddriver.vhd
+batchlab.%: T=batchlab_tb.vhd tb_print7seg.vhd
+batchlab.%: U=lab.ucf
+
+
+# Misc functions that are good to have
+include build/util.mk
+# Setup simulation environment
+include build/vsim.mk
+# Setup synthesis environment
+include build/xst.mk
+# Setup backend flow environment
+include build/xilinx-par.mk
+# Setup tools for programming the FPGA
+include build/digilentprog.mk
+
+
+
+# Alternative synthesis methods
+# The following is for ASIC synthesis
+#include design_compiler.mk
+# The following is for synthesis to a Xilinx target using Precision.
+#include precision-xilinx.mk
+
+
+
diff --git a/lab3/Nexys3_Master.ucf b/lab3/Nexys3_Master.ucf
new file mode 100755
index 0000000..1872ef2
--- /dev/null
+++ b/lab3/Nexys3_Master.ucf
@@ -0,0 +1,277 @@
+## This file is a general .ucf for Nexys3 rev B board

+## To use it in a project:

+## - remove or comment the lines corresponding to unused pins

+## - rename the used signals according to the project

+

+##Clock signal

+#Net "clk" LOC=V10 | IOSTANDARD=LVCMOS33;

+#Net "clk" TNM_NET = sys_clk_pin;

+#TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz;

+

+## onBoard USB controller

+#Net "EppAstb" LOC = H1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L41N_GCLK26_M3DQ5, Sch name = U-FLAGA

+#Net "EppDstb" LOC = K4 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L42P_GCLK25_TRDY2_M3UDM, Sch name = U-FLAGB

+#Net "EppWait" LOC = C2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L83P, Sch name = U-SLRD

+#Net "EppDB<0>" LOC = E1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L50N_M3BA2, Sch name = U-FD0

+#Net "EppDB<1>" LOC = F4 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L51P_M3A10, Sch name = U-FD1

+#Net "EppDB<2>" LOC = F3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L51N_M3A4, Sch name = U-FD2

+#Net "EppDB<3>" LOC = D2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L52P_M3A8, Sch name = U-FD3

+#Net "EppDB<4>" LOC = D1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L52N_M3A9, Sch name = U-FD4

+#Net "EppDB<5>" LOC = H7 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L53P_M3CKE, Sch name = U-FD5

+#Net "EppDB<6>" LOC = G6 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L53N_M3A12, Sch name = U-FD6

+#Net "EppDB<7>" LOC = E4 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L54P_M3RESET, Sch name = U-FD7

+

+#Net "UsbClk" LOC = H2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L41P_GCLK27_M3DQ4, Sch name = U-IFCLK

+#Net "UsbDir" LOC = F6 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L55P_M3A13, Sch name = U-SLCS

+

+#Net "UsbWR" LOC = C1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L83N_VREF, Sch name = U-SLWR

+#Net "UsbOE" LOC = H6 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L49P_M3A7, Sch name = U-SLOE

+

+#Net "UsbAdr<1>" LOC = E3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L50P_M3WE, Sch name = U-FIFOAD1

+#Net "UsbAdr<0>" LOC = H5 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L49N_M3A2, Sch name = U-FIFOAD0

+

+#Net "UsbPktend" LOC = D3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L54N_M3A11, Sch name = U-PKTEND

+

+#Net "UsbFlag" LOC = F5 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L55N_M3A14, Sch name = U-FLAGC

+#Net "UsbMode" LOC = F1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L48N_M3BA1, Sch name = U-INT0#

+

+## onBoard Cellular RAM, Numonyx StrataFlash and Numonyx Quad Flash

+#Net "MemOE" LOC = L18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L46N_FOE_B_M1DQ3, Sch name = P30-OE

+#Net "MemWR" LOC = M16 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L47P_FWE_B_M1DQ0, Sch name = P30-WE

+#Net "MemAdv" LOC = H18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L43N_GCLK4_M1DQ5, Sch name = P30-ADV

+#Net "MemWait" LOC = V4 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L63N, Sch name = P30-WAIT

+#Net "MemClk" LOC = R10 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L29P_GCLK3, Sch name = P30-CLK

+

+#Net "RamCS" LOC = L15 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L42P_GCLK7_M1UDM, Sch name = MT-CE

+#Net "RamCRE" LOC = M18 |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L47N_LDC_M1DQ1, Sch name = MT-CRE

+#Net "RamUB" LOC = K15  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L41P_GCLK9_IRDY1_M1RASN, Sch name = MT-UB

+#Net "RamLB" LOC = K16  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L41N_GCLK8_M1CASN, Sch name = MT-LB

+

+#Net "FlashCS" LOC = L17 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L46P_FCS_B_M1DQ2, Sch name = P30-CE

+#Net "FlashRp" LOC = T4  | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L63P, Sch name = P30-RST

+

+#Net "QuadSpiFlashCS" LOC = V3  | IOSTANDARD = LVCMOS33; #Bank = MISC, pin name = IO_L65N_CSO_B_2, Sch name = CS

+#Net "QuadSpiFlashSck"  LOC = R15 | IOSTANDARD = LVCMOS33; #Bank = MISC, pin name = IO_L1P_CCLK_2, Sch name = SCK

+

+#Net "MemAdr<1>" LOC = K18  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L45N_A0_M1LDQSN, Sch name = P30-A0

+#Net "MemAdr<2>" LOC = K17  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L45P_A1_M1LDQS, Sch name = P30-A1

+#Net "MemAdr<3>" LOC = J18  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L44N_A2_M1DQ7, Sch name = P30-A2

+#Net "MemAdr<4>" LOC = J16  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L44P_A3_M1DQ6, Sch name = P30-A3

+#Net "MemAdr<5>" LOC = G18  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L38N_A4_M1CLKN, Sch name = P30-A4

+#Net "MemAdr<6>" LOC = G16  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L38P_A5_M1CLK, Sch name = P30-A5

+#Net "MemAdr<7>" LOC = H16  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L37N_A6_M1A1, Sch name = P30-A6

+#Net "MemAdr<8>" LOC = H15  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L37P_A7_M1A0, Sch name = P30-A7

+#Net "MemAdr<9>" LOC = H14  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L36N_A8_M1BA1, Sch name = P30-A8

+#Net "MemAdr<10>" LOC = H13  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L36P_A9_M1BA0, Sch name = P30-A9

+#Net "MemAdr<11>" LOC = F18  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L35N_A10_M1A2, Sch name = P30-A10

+#Net "MemAdr<12>" LOC = F17  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L35P_A11_M1A7, Sch name = P30-A11

+#Net "MemAdr<13>" LOC = K13  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L34N_A12_M1BA2, Sch name = P30-A12

+#Net "MemAdr<14>" LOC = K12  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L34P_A13_M1WE, Sch name = P30-A13

+#Net "MemAdr<15>" LOC = E18  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L33N_A14_M1A4, Sch name = P30-A14

+#Net "MemAdr<16>" LOC = E16  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L33P_A15_M1A10, Sch name = P30-A15

+#Net "MemAdr<17>" LOC = G13  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L32N_A16_M1A9, Sch name = P30-A16

+#Net "MemAdr<18>" LOC = H12  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L32P_A17_M1A8, Sch name = P30-A17

+#Net "MemAdr<19>" LOC = D18  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L31N_A18_M1A12, Sch name = P30-A18

+#Net "MemAdr<20>" LOC = D17  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L31P_A19_M1CKE, Sch name = P30-A19

+#Net "MemAdr<21>" LOC = G14  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L30N_A20_M1A11, Sch name = P30-A20

+#Net "MemAdr<22>" LOC = F14  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L30P_A21_M1RESET Sch name = P30-A21

+#Net "MemAdr<23>" LOC = C18  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L29N_A22_M1A14, Sch name = P30-A22

+#Net "MemAdr<24>" LOC = C17  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L29P_A23_M1A13, Sch name = P30-A23

+#Net "MemAdr<25>" LOC = F16  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L1N_A24_VREF, Sch name = P30-A24

+#Net "MemAdr<26>" LOC = F15  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L1P_A25, Sch name = P30-A25

+

+#Net "QuadSpiFlashDB<0>" LOC = T13 |  IOSTANDARD = LVCMOS33; #Dual/Quad SPI Flash DB<0>, Bank = MISC, pin name = IO_L3N_MOSI_CSI_B_MISO0_2, Sch name = SDI

+#Net "MemDB<0>" LOC = R13 |  IOSTANDARD = LVCMOS33; #Ram or Numonyx Paralell Flash DB<0>, or Dual/Quad SPI Flash DB<1>, Bank = MISC, pin name = IO_L3P_D0_DIN_MISO_MISO1_2, Sch name = P30-DQ0

+#Net "MemDB<1>" LOC = T14 |  IOSTANDARD = LVCMOS33; #Ram or Numonyx Paralell Flash DB<1>, or Quad SPI Flash DB<2>, Bank = MISC, pin name = IO_L12P_D1_MISO2_2, Sch name = P30-DQ1

+#Net "MemDB<2>" LOC = V14 |  IOSTANDARD = LVCMOS33; #Ram or Numonyx Paralell Flash DB<2>, or Quad SPI Flash DB<3>, Bank = MISC, pin name = IO_L12N_D2_MISO3_2, Sch name = P30-DQ2

+#Net "MemDB<3>" LOC = U5  |  IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_49P_D3, Sch name = P30-DQ3

+#Net "MemDB<4>" LOC = V5  |  IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_49N_D4, Sch name = P30-DQ4

+#Net "MemDB<5>" LOC = R3  |  IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L62P_D5, Sch name = P30-DQ5

+#Net "MemDB<6>"  LOC = T3  |  IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L62N_D6, Sch name = P30-DQ6

+#Net "MemDB<7>"  LOC = R5  |  IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L48P_D7, Sch name = P30-DQ7

+#Net "MemDB<8>"  LOC = N5  |  IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L64P_D8, Sch name = P30-DQ8

+#Net "MemDB<9>"  LOC = P6  |  IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L64N_D9, Sch name = P30-DQ9

+#Net "MemDB<10>"  LOC = P12 |  IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L13N_D10, Sch name = P30-DQ10

+#Net "MemDB<11>"  LOC = U13 |  IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L14P_D11, Sch name = P30-DQ11

+#Net "MemDB<12>"  LOC = V13 |  IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L14N_D12, Sch name = P30-DQ12

+#Net "MemDB<13>"  LOC = U10 |  IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L30P_GCLK1_D13, Sch name = P30-DQ13

+#Net "MemDB<14>"  LOC = R8  |  IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L31P_GCLK31_D14, Sch name = P30-DQ14

+#Net "MemDB<15>"  LOC = T8  |  IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L31N_GCLK30_D15, Sch name = P30-DQ15

+

+## SMSC ethernet PHY

+#Net "PhyRstn" LOC = P3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L2N, Sch name = ETH-RST

+#Net "PhyCrs" LOC = N3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L1N_VREF, Sch name = ETH-CRS

+#Net "PhyCol" LOC = P4 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L2P, Sch name = ETH-COL

+#Net "PhyClk25Mhz" LOC = N4 | IOSTANDARD = LVCMOS33; #Unconnected if R172 is not loaded, Bank = 3, pin name = IO_L1P, Sch name = ETH-CLK25MHZ

+

+#Net "PhyTxd<3>" LOC = T1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L33N_M3DQ13, Sch name = ETH-TXD3 

+#Net "PhyTxd<2>" LOC  = T2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L33P_M3DQ12, Sch name = ETH-TXD2

+#Net "PhyTxd<1>" LOC = U1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L32N_M3DQ15, Sch name = ETH-TXD1

+#Net "PhyTxd<0>" LOC = U2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L32P_M3DQ14, Sch name = ETH-TXD0

+#Net "PhyTxEn" LOC = L2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L37P_M3DQ0, Sch name = ETH-TX_EN

+#Net "PhyTxClk" LOC = L5 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L43P_GCLK23_M3RASN, Sch name = ETH-TX_CLK

+#Net "PhyTxEr" LOC = P2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L34P_M3UDQS, Sch name = ETH-TXD4

+

+#Net "PhyRxd<3>" LOC = M3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L36P_M3DQ8, Sch name = ETH-RXD3

+#Net "PhyRxd<2>" LOC = N1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L35N_M3DQ11, Sch name = ETH-RXD2

+#Net "PhyRxd<1>" LOC = N2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L35P_M3DQ10, Sch name = ETH-RXD1

+#Net "PhyRxd<0>" LOC = P1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L34N_M3UDQSN, Sch name = ETH-RXD0

+#Net "PhyRxDv" LOC = L1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L37N_M3DQ1, Sch name = ETH-RX_DV

+#Net "PhyRxEr" LOC = M1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L36N_M3DQ9, Sch name = ETH-RXD4

+#Net "PhyRxClk" LOC = H4 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L44P_GCLK21_M3A5, Sch name = ETH-RX_CLK

+

+#Net "PhyMdc" LOC = M5 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L31N_VREF, Sch name = ETH-MDC

+#Net "PhyMdio" LOC = L6 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L31P, Sch name = ETH-MDIO

+

+## Pic USB-HID interface

+#Net "PS2KeyboardData" LOC = J13| IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L39P_M1A3, Sch name = PIC-SDI1

+#Net "PS2KeyboardClk" LOC = L12 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L40P_GCLK11_M1A5, Sch name = PIC-SCK1

+

+#NET "PS2MouseData" LOC = K14 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L39N_M1ODT, Sch name = PIC-SDO1

+#NET "PS2MouseClk" LOC = L13| IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L40N_GCLK10_M1A6, Sch name = PIC-SS1

+

+#Net "PicGpio<0>" LOC = L16 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L42N_GCLK6_TRDY1_M1LDM, Sch name = PIC-GPIO0

+#NET "PicGpio<1>" LOC = H17 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L43P_GCLK5_M1DQ4, Sch name = PIC-GPIO1

+

+## Usb-RS232 interface

+#Net "RxD" LOC = N17 | IOSTANDARD=LVCMOS33; #Bank = 1, pin name = IO_L48P_HDC_M1DQ8, Sch name = MCU-RX

+#Net "TxD" LOC = N18 | IOSTANDARD=LVCMOS33; #Bank = 1, pin name = IO_L48N_M1DQ9, Sch name = MCU-TX

+

+## 7 segment display

+#Net "seg<0>" LOC = T17 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L51P_M1DQ12, Sch name = CA

+#Net "seg<1>" LOC = T18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L51N_M1DQ13, Sch name = CB

+#Net "seg<2>" LOC = U17 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L52P_M1DQ14, Sch name = CC

+#Net "seg<3>" LOC = U18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L52N_M1DQ15, Sch name = CD

+#Net "seg<4>" LOC = M14 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L53P, Sch name = CE

+#Net "seg<5>" LOC = N14 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L53N_VREF, Sch name = CF

+#Net "seg<6>" LOC = L14 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L61P, Sch name = CG

+#Net "seg<7>" LOC = M13 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L61N, Sch name = DP

+

+#Net "an<0>" LOC = N16 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L50N_M1UDQSN, Sch name = AN0

+#Net "an<1>" LOC = N15 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L50P_M1UDQS, Sch name = AN1

+#Net "an<2>" LOC = P18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L49N_M1DQ11, Sch name = AN2

+#Net "an<3>" LOC = P17 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L49P_M1DQ10, Sch name = AN3

+

+## Leds

+#Net "Led<0>" LOC = U16 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L2P_CMPCLK, Sch name = LD0

+#Net "Led<1>" LOC = V16 |  IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L2N_CMPMOSI, Sch name = LD1

+#Net "Led<2>" LOC = U15 |  IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L5P, Sch name = LD2

+#Net "Led<3>" LOC = V15 |  IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L5N, Sch name = LD3

+#Net "Led<4>" LOC = M11 |  IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L15P, Sch name = LD4

+#Net "Led<5>" LOC = N11 |  IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L15N, Sch name = LD5

+#Net "Led<6>" LOC = R11 |  IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L16P, Sch name = LD6

+#Net "Led<7>" LOC = T11 |  IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L16N_VREF, Sch name = LD7

+

+## Switches

+#Net "sw<0>" LOC = T10 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L29N_GCLK2, Sch name = SW0

+#Net "sw<1>" LOC = T9 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L32P_GCLK29, Sch name = SW1

+#Net "sw<2>" LOC = V9 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L32N_GCLK28, Sch name = SW2

+#Net "sw<3>" LOC = M8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L40P, Sch name = SW3

+#Net "sw<4>" LOC = N8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L40N, Sch name = SW4

+#Net "sw<5>" LOC = U8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L41P, Sch name = SW5

+#Net "sw<6>" LOC = V8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L41N_VREF, Sch name = SW6

+#Net "sw<7>" LOC = T5 | IOSTANDARD = LVCMOS33; #Bank = MISC, pin name = IO_L48N_RDWR_B_VREF_2, Sch name = SW7

+

+## Buttons

+#Net "btns" LOC = B8 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L33P, Sch name = BTNS

+#Net "btnu" LOC = A8 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L33N, Sch name = BTNU

+#Net "btnl" LOC = C4 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L1N_VREF, Sch name = BTNL

+#Net "btnd" LOC = C9 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L34N_GCLK18, Sch name = BTND

+#Net "btnr" LOC = D9 | IOSTANDARD = LVCMOS33; # Bank = 0, pin name = IO_L34P_GCLK19, Sch name = BTNR

+

+## VGA Connector

+#NET "vgaRed<0> LOC = U7 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L43P, Sch name = RED0

+#NET "vgaRed<1> LOC = V7 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L43N, Sch name = RED1

+#NET vgaRed<2> LOC = N7 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L44P, Sch name = RED2

+#NET vgaGreen<0> LOC = P8 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L44N, Sch name = GRN0

+#NET vgaGreen<1> LOC = T6 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L45P, Sch name = GRN1

+#NET vgaGreen<2> LOC = V6 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L45N, Sch name = GRN2

+#NET vgaBlue<1> LOC = R7 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L46P, Sch name = BLU1

+#NET vgaBlue<2> LOC = T7 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L46N, Sch name = BLU2

+

+#NET "Hsync" LOC = N6 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L47P, Sch name = HSYNC

+#NET "Vsync" LOC = P7 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L47N, Sch name = VSYNC

+

+## 12 pin connectors

+

+##JA

+#Net "JA<0>" LOC = T12 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L19P, Sch name = JA1

+#Net "JA<1>" LOC = V12 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L19N, Sch name = JA2  

+#Net "JA<2>" LOC = N10 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L20P, Sch name = JA3

+#Net "JA<3>" LOC = P11 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L20N, Sch name = JA4

+#Net "JA<4>" LOC = M10 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L22P, Sch name = JA7

+#Net "JA<5>" LOC = N9 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L22N, Sch name = JA8

+#Net "JA<6>" LOC = U11 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L23P, Sch name = JA9

+#Net "JA<7>" LOC = V11 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L23N, Sch name = JA10

+

+##JB

+#Net "JB<0>" LOC = K2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L38P_M3DQ2, Sch name = JB1

+#Net "JB<1>" LOC = K1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L38N_M3DQ3, Sch name = JB2

+#Net "JB<2>" LOC = L4 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L39P_M3LDQS, Sch name = JB3

+#Net "JB<3>" LOC = L3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L39N_M3LDQSN, Sch name = JB4

+#Net "JB<4>" LOC = J3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L40P_M3DQ6, Sch name = JB7

+#Net "JB<5>" LOC = J1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L40N_M3DQ7, Sch name = JB8

+#Net "JB<6>" LOC = K3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L42N_GCLK24_M3LDM, Sch name = JB9

+#Net "JB<7>" LOC = K5 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L43N_GCLK22_IRDY2_M3CASN, Sch name = JB10

+

+##JC

+#Net "JC<0>" LOC = H3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L44N_GCLK20_M3A6, Sch name = JC1

+#Net "JC<1>" LOC = L7 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L45P_M3A3, Sch name = JC2

+#Net "JC<2>" LOC = K6 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L45N_M3ODT, Sch name = JC3

+#Net "JC<3>" LOC = G3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L46P_M3CLK, Sch name = JC4

+#Net "JC<4>" LOC = G1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L46N_M3CLKN, Sch name = JC7

+#Net "JC<5>" LOC = J7 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L47P_M3A0, Sch name = JC8

+#Net "JC<6>" LOC = J6 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L47N_M3A1, Sch name = JC9

+#Net "JC<7>" LOC = F2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L48P_M3BA0, Sch name = JC10

+

+##JD, LX16 Die only

+#Net "JD<0>" LOC = G11 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L40P, Sch name = JD1

+#Net "JD<1>" LOC = F10 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L40N, Sch name = JD2

+#Net "JD<2>" LOC = F11 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L42P, Sch name = JD3

+#Net "JD<3>" LOC = E11 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L42N, Sch name = JD4

+#Net "JD<4>" LOC = D12 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L47P, Sch name = JD7

+#Net "JD<5>" LOC = C12 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L47N, Sch name = JD8

+#Net "JD<6>" LOC = F12 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L51P, Sch name = JD9

+#Net "JD<7>" LOC = E12 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L51N, Sch name = JD10

+

+## VHDCI Connector

+#Net "EXP-IO_P<0>" LOC = B2 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L2P, Sch name = EXP_IO1_P

+#Net "EXP-IO_N<0>" LOC = A2 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L2N, Sch name = EXP_IO1_N

+#Net "EXP-IO_P<1>" LOC = D6 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L3P, Sch name = EXP_IO2_P

+#Net "EXP-IO_N<1>" LOC = C6 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L3N, Sch name = EXP_IO2_N

+#Net "EXP-IO_P<2>" LOC = B3 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L4P, Sch name = EXP_IO3_P

+#Net "EXP-IO_N<2>" LOC = A3 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L4N, Sch name = EXP_IO3_N

+#Net "EXP-IO_P<3>" LOC = B4 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L5P, Sch name = EXP_IO4_P

+#Net "EXP-IO_N<3>" LOC = A4 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L5N, Sch name = EXP_IO4_N

+#Net "EXP-IO_P<4>" LOC = C5 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L6P, Sch name = EXP_IO5_P

+#Net "EXP-IO_N<4>" LOC = A5 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L6N, Sch name = EXP_IO5_N

+#Net "EXP-IO_P<5>" LOC = B6 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L8P, Sch name = EXP_IO6_P

+#Net "EXP-IO_N<5>" LOC = A6 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L8N_VREF, Sch name = EXP_IO6_N

+#Net "EXP-IO_P<6>" LOC = C7 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L10P, Sch name = EXP_IO7_P

+#Net "EXP-IO_N<6>" LOC = A7 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L10N, Sch name = EXP_IO7_N

+#Net "EXP-IO_P<7>" LOC = D8 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L11P, Sch name = EXP_IO8_P

+#Net "EXP-IO_N<7>" LOC = C8 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L11N, Sch name = EXP_IO8_N

+#Net "EXP-IO_P<8>" LOC = B9 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L35P_GCLK17, Sch name = EXP_IO9_P

+#Net "EXP-IO_N<8>" LOC = A9 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L35N_GCLK16, Sch name = EXP_IO9_N

+#Net "EXP-IO_P<9>" LOC = D11 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L36P_GCLK15, Sch name = EXP_IO10_P

+#Net "EXP-IO_N<9>" LOC = C11 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L36N_GCLK14, Sch name = EXP_IO10_N

+#Net "EXP-IO_P<10>" LOC = C10 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L37P_GCLK13, Sch name = EXP_IO11_P

+#Net "EXP-IO_N<10>" LOC = A10 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L37N_GCLK12, Sch name = EXP_IO11_N

+#Net "EXP-IO_P<11>" LOC = G9 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L38P, Sch name = EXP_IO12_P

+#Net "EXP-IO_N<11>" LOC = F9 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L38N_VREF, Sch name = EXP_IO12_N

+#Net "EXP-IO_P<12>" LOC = B11 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L39P, Sch name = EXP_IO13_P

+#Net "EXP-IO_N<12>" LOC = A11 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L39N, Sch name = EXP_IO13_N

+#Net "EXP-IO_P<13>" LOC = B12 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L41P, Sch name = EXP_IO14_P

+#Net "EXP-IO_N<13>" LOC = A12 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L41N, Sch name = EXP_IO14_N

+#Net "EXP-IO_P<14>" LOC = C13 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L50P, Sch name = EXP_IO15_P

+#Net "EXP-IO_N<14>" LOC = A13 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L50N, Sch name = EXP_IO15_N

+#Net "EXP-IO_P<15>" LOC = B14 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L62P, Sch name = EXP_IO16_P

+#Net "EXP-IO_N<15>" LOC = A14 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L62N_VREF, Sch name = EXP_IO16_N

+#Net "EXP-IO_P<16>" LOC = F13 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L63P_SCP7, Sch name = EXP_IO17_P

+#Net "EXP-IO_N<16>" LOC = E13 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L63N_SCP6, Sch name = EXP_IO17_N

+#Net "EXP-IO_P<17>" LOC = C15 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L64P_SCP5, Sch name = EXP_IO18_P

+#Net "EXP-IO_N<17>" LOC = A15 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L64N_SCP4, Sch name = EXP_IO18_N

+#Net "EXP-IO_P<18>" LOC = D14 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L65P_SCP3, Sch name = EXP_IO19_P

+#Net "EXP-IO_N<18>" LOC = C14 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L65N_SCP2, Sch name = EXP_IO19_N

+#Net "EXP-IO_P<19>" LOC = B16 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L66P_SCP1, Sch name = EXP_IO20_P

+#Net "EXP-IO_N<19>" LOC = A16 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L66N_SCP0, Sch name = EXP_IO20_N

diff --git a/lab3/build/dc_synthesize.tcl b/lab3/build/dc_synthesize.tcl
new file mode 100755
index 0000000..45afc74
--- /dev/null
+++ b/lab3/build/dc_synthesize.tcl
@@ -0,0 +1,95 @@
+sh date
+
+# set some per design variables FIXME - use these!
+# set LOG_PATH  "synth/dc_test_synth/log/"
+# set GATE_PATH "synth/dc_test_synth/gate/"
+# set RTL_PATH  "synth/dc_test_synth/verilog/"
+
+# Should be moved to a synthesis setup dot file?
+set target_library {/sw/mentor/libraries/cmos065_522/CORE65LPLVT_5.1/libs/CORE65LPLVT_nom_1.20V_25C.db}
+set link_library $target_library 
+
+
+
+proc dir_exists {name} {
+    if { [catch {set type [file type $name] } ]  } {
+	return 0;
+    } 
+    if { $type == "directory" } {
+	return 1;
+    }
+    return 0;
+
+}
+
+source designinfo.tcl
+
+
+if {[dir_exists $TOPLEVEL.out]} {
+    sh rm -r ./$TOPLEVEL.out
+}
+sh mkdir ./$TOPLEVEL.out
+
+set power_preserve_rtl_hier_names true
+
+
+current_design $TOPLEVEL
+
+elaborate $TOPLEVEL
+
+# Set timing constaints, this says that a max of .5ns of delay from
+# input to output is allowable 
+#set_max_delay .1 -from [all_inputs] -to [all_outputs]
+
+
+# If this were a clocked piece of logic we could set a clock
+#  period to shoot for like this 
+set_clock_gating_style  -max_fanout 16
+
+# Some default settings, you probably need to change this for your
+# particular project!
+create_clock clk -period 2
+set_input_delay -clock clk 0.1 [all_inputs]
+set_output_delay -clock clk 0.1 [all_outputs]
+
+
+
+# FIXME - check this!
+#optimize_registers -sync_trans multiclass 
+
+# Check for warnings/errors 
+check_design
+
+# ungroup everything 
+ungroup -flatten -all
+
+# flatten it all, this forces all the hierarchy to be flattened out 
+set_flatten true -effort high
+uniquify
+
+# This forces the compiler to spend as much effort (and time)
+# compiling this RTL to achieve timing possible. 
+#
+# Clock gating is enabled by default to reduce power.
+compile_ultra -gate_clock
+
+# Now that the compile is complete report on the results 
+
+check_design > ./$TOPLEVEL.out/check_design.rpt
+
+report_constraint -all_violators -verbose  > constraint.rpt
+report_wire_load > wire_load_model_used.rpt
+report_area > area.rpt
+report_qor > qor.rpt
+report_timing -max_paths 1000 > timing.rpt
+
+
+report_ultra_optimization > ultraopt.rpt
+report_power -verbose > power_estimate.rpt
+report_design > ./$TOPLEVEL.out/design_information.rpt
+report_resources > ./$TOPLEVEL.out/resources.rpt
+
+# Finally write the post synthesis netlist out to a verilog file 
+write -f verilog -output synthesized_netlist.v -hierarchy
+
+quit
diff --git a/lab3/build/design_compiler.mk b/lab3/build/design_compiler.mk
new file mode 100755
index 0000000..35ed335
--- /dev/null
+++ b/lab3/build/design_compiler.mk
@@ -0,0 +1,30 @@
+
+$(PROJNAME)-synthdir/dc/synth/synth.tcl: build/dc_synthesize.tcl
+	@echo
+	@echo '*** Copying synthesis script ***'
+	@echo
+	mkdir -p $(@D)
+	cp build/dc_synthesize.tcl $(@D)/synth.tcl
+
+$(PROJNAME)-synthdir/dc/synth/designinfo.tcl: $(S)
+	@echo
+	@echo '*** Generate design info script ***'
+	@echo
+	mkdir -p $(@D)
+	rm -f $(@D)/designtmp
+	echo 'set TOPLEVEL '$$(basename $$(echo $(firstword $(S)) | sed 's/\..*$$//')) >> $@.tmp
+	$(foreach i,$(filter %.v,$(S)), echo 'read_verilog "$(call fixpath3,$(i))"' >> $@.tmp;)
+	$(foreach i,$(filter %.sv,$(S)), echo 'read_sverilog "$(call fixpath3,$(i))"' >> $@.tmp;)
+	$(foreach i,$(filter %.vhd,$(S)), echo 'read_vhdl "$(call fixpath3,$(i))"' >> $@.tmp;)
+	$(foreach i,$(filter %.vhdl,$(S)), echo 'read_vhdl "$(call fixpath3,$(i))"' >> $@.tmp;)
+	$(foreach i,$(filter %.v,$(S)), echo 'analyze -format verilog "$(call fixpath3,$(i))"' >> $@.tmp;)
+	$(foreach i,$(filter %.sv,$(S)), echo 'analyze -format sverilog "$(call fixpath3,$(i))"' >> $@.tmp;)
+	$(foreach i,$(filter %.vhd,$(S)), echo 'analyze -format vhdl "$(call fixpath3,$(i))"' >> $@.tmp;)
+	$(foreach i,$(filter %.vhdl,$(S)), echo 'analyze -format vhdl "$(call fixpath3,$(i))"' >> $@.tmp;)
+	mv $@.tmp $@
+
+$(PROJNAME)-synthdir/dc/synth/design.v: $(PROJNAME)-synthdir/dc/synth/synth.tcl $(PROJNAME)-synthdir/dc/synth/designinfo.tcl $(S)
+	cd $(PROJNAME)-synthdir/dc/synth; dc_shell -f synth.tcl
+
+%.synth: 
+	$(NICE) $(MAKE) -f $(firstword $(MAKEFILE_LIST)) $*-synthdir/dc/synth/design.v  PROJNAME="$*"
diff --git a/lab3/build/digilentprog.mk b/lab3/build/digilentprog.mk
new file mode 100755
index 0000000..8f55a5e
--- /dev/null
+++ b/lab3/build/digilentprog.mk
@@ -0,0 +1,6 @@
+
+PROG:
+	djtgcfg prog -i 0 -d Nexys3 -f $(PROJNAME)-synthdir/layoutdefault/design.bit
+
+%.prog:
+	$(NICE) $(MAKE) -f Makefile PROG PROJNAME="$*"
diff --git a/lab3/build/precision-xilinx.mk b/lab3/build/precision-xilinx.mk
new file mode 100755
index 0000000..fafa3bc
--- /dev/null
+++ b/lab3/build/precision-xilinx.mk
@@ -0,0 +1,59 @@
+PRECISION=precision
+
+# FIXME - different directoreis for different synthesis scripts?
+# For precision:
+$(PROJNAME)-synthdir/synth/precision/design.scr: $(S) | dump_synthsettings
+	@echo
+	@echo '*** Creating synthesis scripts for Precision ***'
+	@echo
+	mkdir -p $(@D)
+	rm -f $(@D)/design.scr;
+	echo set_results_dir . > $(@D)/design.scr
+	echo -n 'add_input_file {' >> $(@D)/design.scr
+	for i in $(S); do echo -n " \"$$PWD/$$i\"" >> $(@D)/design.scr; done
+	echo '}' >> $(@D)/design.scr
+	echo "setup_design -design "$$(basename $$(echo $(firstword $(S)) | sed 's/\..*$$//')) >> $(@D)/design.scr
+	echo 'setup_design -manufacturer $(PRECISION_MANUFACTURER) -family $(PRECISION_FAMILY)  -part $(PRECISION_PART) -speed $(PRECISION_SPEEDGRADE)' >> $(@D)/design.scr
+	echo '$(PRECISION_EXTRA_OPTIONS)'  >> $(@D)/design.scr
+	echo 'setup_design -basename design' >> $(@D)/design.scr
+	echo 'compile' >> $(@D)/design.scr
+	echo 'synthesize' >> $(@D)/design.scr
+	echo 'report_area > area.rpt' >> $(@D)/design.scr
+
+$(PROJNAME)-synthdir/synth/precision/design.edf: $(PROJNAME)-synthdir/synth/precision/design.scr
+	cd $(@D);$(NICE) $(PRECISION) -shell -file design.scr
+
+$(PROJNAME)-synthdir/synth/design.edf: $(PROJNAME)-synthdir/synth/precision/design.edf
+	cp $< $@
+
+dump_synthsettings:
+	@echo
+	@echo "   *** Important settings for the Synthesis module ***"
+	@echo
+	@echo "   Synthesis top module: $$(basename $$(echo $(firstword $(S)) | sed 's/\..*$$//'))"
+	@echo "   Files to synthesize:  $(S)"
+	@echo "   Include directories: $(INCDIRS)"
+	@echo "   FPGA part (PRECISION_PART): $(PRECISION_PART)"
+	@echo "   FPGA familypart (PRECISION_FAMILY): $(PRECISION_FAMILY)"
+	@echo "   FPGA manufacturer (PRECISION_MANUFACTURER): $(PRECISION_MANUFACTURER)"
+	@echo "   FPGA speedgrade (PRECISION_SPEEDGRADE): $(PRECISION_SPEEDGRADE)"
+	@echo "   Extra options to precision: $(PRECISION_EXTRA_OPTIONS)"
+	@echo
+
+export PRECISION_PART
+export PRECISION_FAMILY
+export PRECISION_MANUFACTURER
+export PRECISION_SPEEDGRADE
+export PRECISION_EXTRA_OPTIONS
+
+# How to handle EDN files?
+# $(PROJNAME)-synthdir/layoutdefault/design.ngd: $(PROJNAME)-synthdir/synth/design.ngc $(U)
+#     $(@D)/%.ngd: $(@D)/%.edf %.ucf
+#     	rm -rf $(@D)/_ngo
+#     	mkdir $(@D)/_ngo
+#     	cp *.edn $(@D)
+#     	cd $(@D); $(XILINX_INIT) ngdbuild -dd _ngo -nt timestamp -p $(PART) -uc $(PWD)/$*.ucf $*.edf  $*.ngd
+
+
+%.synth:
+	$(NICE) $(MAKE) -f $(firstword $(MAKEFILE_LIST)) $*-synthdir/synth/precision/design.edf  PROJNAME="$*"
diff --git a/lab3/build/util.mk b/lab3/build/util.mk
new file mode 100755
index 0000000..3bc84ca
--- /dev/null
+++ b/lab3/build/util.mk
@@ -0,0 +1,59 @@
+# Make sure we can include this from more than one place without any
+# issues:
+ifneq ($(UTILISINCLUDED),1)
+
+
+# The default shell for make is /bin/sh which doesn't work for some of
+# the commands used in these files.
+SHELL=/bin/bash
+
+
+# Make sure we are running at low priority...
+NICE = nice -n 19
+
+# Reverses the order of all arguments given to the function.
+reverse_order = $(if $(1), $(word $(words $(1)),$(1)) $(call reverse_order,$(wordlist 2,$(words $(1)),dummy $(1))),$(1))
+
+# Fix the path by inserting ../../.. if the path is relative. If absolute, do nothing
+fixpath3 = $(shell echo "$(1)" | sed 's,^\([^/]\),../../../\1,')
+
+# Fix the path by inserting ../.. if the path is relative. If absolute, do nothing
+fixpath2 = $(shell echo "$(1)" | sed 's,^\([^/]\),../../\1,')
+
+
+# Fix the path by inserting ../ if the path is relative. If absolute, do nothing
+fixpath1 = $(shell echo "$(1)" | sed 's,^\([^/]\),../\1,')
+
+export S
+export INCDIRS
+export T
+export U
+export PART
+export PROJNAME
+
+
+sanitycheckclock:
+	$(foreach i,$(S), bash sanitycheck.sh "$(i)" &&) true
+
+sanitychecksynth: sanitycheckclock
+	@if [ "$(S)" == "" ]; then echo 'ERROR: No synthesizable files specified!';false;fi
+
+sanitychecktb: sanitycheckclock
+	@if [ "$(T)" == "" ]; then echo 'ERROR: No testbench files specified!';false;fi
+	@if [ "$(S)" == "" ]; then echo 'WARNING: No synthesizable files specified!';fi
+
+
+
+%.clean:
+	rm -rf "$*-synthdir" "$*-simdir"
+
+
+
+clean:
+	rm -rf *synthdir *simdir *~
+
+
+
+UTILISINCLUDED=1
+endif
+
diff --git a/lab3/build/vsim.mk b/lab3/build/vsim.mk
new file mode 100755
index 0000000..a15219b
--- /dev/null
+++ b/lab3/build/vsim.mk
@@ -0,0 +1,61 @@
+# Needed for modelsim compilation of VHDL files
+T_REV=$(call reverse_order,$(T))
+S_REV=$(call reverse_order,$(S))
+
+#Enable this to set coverage...
+#COVERAGE=-cover bcst
+#FIXME - INCDIR handling
+
+VERILOGCOMPILE=vlog +acc $(COVERAGE) $(INCDIR)
+VHDLCOMPILE=vcom +acc $(COVERAGE)
+BATCHSIM?=vsim -c -do 'run -a;quit -f'
+GUISIM?=vsim
+
+# TODO: Don't recompile all files all the time!
+# (Re)compile all files used for the testbench
+
+$(PROJNAME)-simdir/work:
+	mkdir -p $(PROJNAME)-simdir
+	cd $(PROJNAME)-simdir;vlib work
+
+SIMTBFILES: $(PROJNAME)-simdir/work $(T_REV)
+	$(if $(filter %.vhd,$(T_REV)),  cd $(PROJNAME)-simdir; $(VHDLCOMPILE)	 $(foreach i, $(filter %.vhd, $(T_REV)), $(call fixpath1,$(i))))
+	$(if $(filter %.vhdl,$(T_REV)), cd $(PROJNAME)-simdir; $(VHDLCOMPILE)	 $(foreach i, $(filter %.vhdl, $(T_REV)), $(call fixpath1,$(i))))
+	$(if $(filter %.v,$(T_REV)),    cd $(PROJNAME)-simdir; $(VERILOGCOMPILE) $(foreach i, $(filter %.v, $(T_REV)), $(call fixpath1,$(i))))
+	$(if $(filter %.sv,$(T_REV)),   cd $(PROJNAME)-simdir; $(VERILOGCOMPILE) $(foreach i, $(filter %.sv, $(T_REV)), $(call fixpath1,$(i))))
+
+SIMSYNTHFILES: $(PROJNAME)-simdir/work $(S_REV)			
+	$(if $(filter %.vhd,$(S_REV)),  cd $(PROJNAME)-simdir; $(VHDLCOMPILE)	 $(foreach i, $(filter %.vhd, $(S_REV)), $(call fixpath1,$(i))))
+	$(if $(filter %.vhdl,$(S_REV)), cd $(PROJNAME)-simdir; $(VHDLCOMPILE)	 $(foreach i, $(filter %.vhdl, $(S_REV)), $(call fixpath1,$(i))))
+	$(if $(filter %.v,$(S_REV)),    cd $(PROJNAME)-simdir; $(VERILOGCOMPILE) $(foreach i, $(filter %.v, $(S_REV)), $(call fixpath1,$(i))))
+	$(if $(filter %.sv,$(S_REV)),   cd $(PROJNAME)-simdir; $(VERILOGCOMPILE) $(foreach i, $(filter %.sv, $(S_REV)), $(call fixpath1,$(i))))
+
+
+SIMFILES: SIMSYNTHFILES SIMTBFILES sanitychecktb sanitycheck
+
+# FIXME - How to handle for example  -L unisim ?
+SIM: SIMFILES
+	cd $(PROJNAME)-simdir;$(GUISIM) $$(basename $$(echo $(firstword $(T)) | sed 's/\..*$$//'))
+
+SIMC: SIMFILES
+	cd $(PROJNAME)-simdir; $(BATCHSIM) $$(basename $$(echo $(firstword $(T)) | sed 's/\..*$$//'))
+
+
+#	vcom  +acc $(PROJNAME)-synthdir/xst/synth//design_postsynth.vhd
+SYNTHSIMC: $(POSTSYNTHSIMNETLIST) SIMTBFILES
+	echo $*
+	$(NICE) $(MAKE) -f Makefile SIMC S="$(POSTSYNTHSIMNETLIST)" PROJNAME=$(PROJNAME) BATCHSIM="$(BATCHSIM) $(MODELSIM_POSTSYNTH_OPTIONS)"
+
+
+
+%.simfiles:
+	$(NICE) $(MAKE) -f Makefile SIMFILES PROJNAME="$*"
+
+%.sim:
+	$(NICE) $(MAKE) -f Makefile SIM PROJNAME="$*"
+
+%.simc:
+	$(NICE) $(MAKE) -f Makefile SIMC PROJNAME="$*"
+
+%.synthsimc:
+	$(NICE) $(MAKE) -f Makefile SYNTHSIMC PROJNAME="$*" 
diff --git a/lab3/build/xilinx-par.mk b/lab3/build/xilinx-par.mk
new file mode 100755
index 0000000..f178422
--- /dev/null
+++ b/lab3/build/xilinx-par.mk
@@ -0,0 +1,137 @@
+# FIXME - rule to create ngd file from edf file as well...
+
+dump_backendsettings:
+	@echo
+	@echo "   *** Important settings for the Xilinx Backend module ***"
+	@echo
+	@echo "   Synthesis top module: $$(basename $$(echo $(firstword $(S)) | sed 's/\..*$$//'))"
+	@echo "   FPGA part (PART): $(PART)"
+	@echo "   Constraints file: $(U)"
+	@echo
+
+
+# This is the default rule for NGDBuild when we are not trying to override our TIMESPEC
+$(PROJNAME)-synthdir/layoutdefault/%.ngd: $(PROJNAME)-synthdir/synth/design.ngc $(U) 
+	@echo
+	@echo '*** Producing NGD file ***'
+	@echo
+	rm -rf $(@D)/_ngo
+	mkdir -p $(@D)/_ngo
+# Running ngdbuild without any UCF file
+	if [ "$(U)" == "" ]; then \
+		cd $(@D); $(XILINX_INIT) ngdbuild -sd . -dd _ngo -nt timestamp -p $(PART) ../synth/design.ngc  design.ngd;\
+	else \
+		cd $(@D); $(XILINX_INIT) ngdbuild -sd . -dd _ngo -nt timestamp -p $(PART) -uc $(call fixpath2,$(U)) ../synth/design.ngc  design.ngd;\
+	fi
+
+
+# This is the default rule for NGDBuild when we are not trying to override our TIMESPEC
+$(PROJNAME)-synthdir/layoutdefault/%.ngd: $(PROJNAME)-synthdir/synth/design.edf $(U)
+	@echo
+	@echo '*** Producing NGD file ***'
+	@echo
+	rm -rf $(@D)/_ngo
+	mkdir -p $(@D)/_ngo
+# Running ngdbuild without any UCF file
+	if [ "$(U)" == "" ]; then \
+		cd $(@D); $(XILINX_INIT) ngdbuild -sd . -dd _ngo -nt timestamp -p $(PART) ../synth/design.edf  design.ngd;\
+	else \
+		cd $(@D); $(XILINX_INIT) ngdbuild -sd . -dd _ngo -nt timestamp -p $(PART) -uc $(call fixpath2,$(U)) ../synth/design.edf  design.ngd;\
+	fi
+
+
+# This is the rule for NGDBuild when we are trying to override the TIMESPEC when using a project.fmax rule
+$(PROJNAME)-synthdir/layout%/design.ngd: $(PROJNAME)-synthdir/synth/design.ngc $(U)
+	@echo
+	@echo '*** Producing NGD file ***'
+	@echo
+	rm -rf $(@D)/_ngo
+	mkdir -p $(@D)/_ngo
+	@if [ "$(U)" == "" ]; then \
+            echo 'Cannot synthesize to a specific MHz without a UCF file'; false; \
+        fi
+
+# At this point we try to override the default time constraint!
+	@if ! [ $$(grep -i TIMESPEC $(U) | wc -l) -eq 1 ]; then echo The script can only handle one timespec for now.;false;fi
+	@if ! egrep -q '^TIMESPEC ".*" *= *PERIOD *".*" *[0-9\.]+ *ns *HIGH *50 *% *;' $(U);then\
+            echo 'TIMESPEC line in UCF must be in the following format: TIMESPEC "name" = PERIOD 4.5 ns HIGH 50%;';\
+	    false;\
+        fi
+	sed 's/^\(TIMESPEC *".*" *= *PERIOD *".*"\) *[0-9\.]\+ *ns *HIGH  *50 *%; *$$/\1 $* HIGH 50%;/' < $(U) > $(@D)/design.ucf
+	@echo "*** UCF file setup for timespec $* ***"
+	cd $(@D); $(XILINX_INIT) ngdbuild -sd . -dd _ngo -nt timestamp -p $(PART) -uc design.ucf  ../synth/design.ngc  design.ngd
+
+
+
+# Map a design into the FPGA components
+$(PROJNAME)-synthdir/layout%/design_map.ncd $(PROJNAME)-synthdir/layout%/design.pcf: $(PROJNAME)-synthdir/layout%/design.ngd
+	@echo
+	@echo '*** Mapping design ***'
+	@echo
+	cd $(@D);$(XILINX_INIT) map -detail -u -p  $(PART) -pr b -c 100 -o design_map.ncd design.ngd design.pcf
+
+# Rule for placing and routing a design
+$(PROJNAME)-synthdir/layout%/design.ncd: $(PROJNAME)-synthdir/layout%/design_map.ncd $(PROJNAME)-synthdir/layout%/design.pcf
+	@echo
+	@echo '*** Routing design ***'
+	@echo
+	cd $(@D); $(XILINX_INIT) par -nopad -w  -ol high design_map.ncd design.ncd design.pcf 
+
+$(PROJNAME)-synthdir/layoutdefault/design_postpar.vhd: $(PROJNAME)-synthdir/layoutdefault/design.ncd
+	@echo
+	@echo '*** Creating post place and route netlist $* ***'
+	@echo
+	$(XILINX_INIT) netgen -w -ofmt vhdl $(@D)/design.ncd $@
+
+
+
+$(PROJNAME)-synthdir/layout%/design.twr: $(PROJNAME)-synthdir/layout%/design.ncd
+	@echo
+	@echo '*** Running static timing analysis ***'
+	@echo
+	cd $(@D); $(XILINX_INIT) trce -v 1000 design.ncd design.pcf
+
+$(PROJNAME)-synthdir/layoutdefault/design.xdl: work $(PROJNAME)-synthdir/layoutdefault/design.ncd
+	@echo
+	@echo '*** Creating XDL netlist ***'
+	@echo
+	cd $(@D); $(XILINX_INIT) xdl -w -ncd2xdl design.ncd
+
+
+$(PROJNAME)-synthdir/layoutdefault/design.bit: $(PROJNAME)-synthdir/layoutdefault/design.ncd
+	cd $(@D); $(XILINX_INIT) bitgen -w design.ncd
+
+
+# Duplicate the layout dependencies a couple of time with different
+# timespecs to enable parallel make to investigate several different
+# timing specs simultaneously on multi processor machines.
+#
+# Warning: You may have a limited amount of licenses for ISE!
+expandtimespec = $(shell echo 'scale=5;for(i=0;i<25;i+=1){$(1)-i*0.1;print " "}'|bc)
+$(PROJNAME)-synthdir/fmax.rpt: $(foreach i,$(call expandtimespec,$(TIMESPEC)),$(PROJNAME)-synthdir/layout$(i)/design.twr)
+	@echo 
+	@echo '*** Maximum frequencies follow ***'
+	@echo 
+	grep MHz $(PROJNAME)-synthdir/layout*/design.twr
+
+
+# The rules below are the only rules that are expected to actually be
+# called by a normal user of this makefile.
+
+%.bitgen: dump_backendsettings
+	$(NICE) $(MAKE) -f Makefile $*-synthdir/layoutdefault/design.bit PROJNAME="$*" S="$(S)" U="$(U)" XST_OPT="$(XST_OPT)" PART="$(PART)" INCDIRS="$(INCDIRS)"
+
+%.fmax: dump_backendsettings
+	$(NICE) $(MAKE) -f Makefile $*-synthdir/fmax.rpt  PROJNAME="$*" S="$(S)" U="$(U)" XST_OPT="$(XST_OPT)" PART="$(PART)" TIMESPEC=$(TIMESPEC) INCDIRS="$(INCDIRS)"
+
+
+
+%.route: dump_backendsettings
+	$(NICE) $(MAKE) -f Makefile $*-synthdir/layoutdefault/design.ncd  PROJNAME="$*" S="$(S)" U="$(U)" XST_OPT="$(XST_OPT)" PART="$(PART)" INCDIRS="$(INCDIRS)"
+
+%.timing: dump_backendsettings
+	$(NICE) $(MAKE) -f Makefile $*-synthdir/layoutdefault/design.twr PROJNAME="$*" S="$(S)" U="$(U)" XST_OPT="$(XST_OPT)" PART="$(PART)" INCDIRS="$(INCDIRS)"
+
+%.xdl: dump_backendsettings
+	$(NICE) $(MAKE) -f Makefile $*-synthdir/layoutdefault/design.xdl PROJNAME="$*" S="$(S)" U="$(U)" XST_OPT="$(XST_OPT)" PART="$(PART)" T="$(T)" INCDIRS="$(INCDIRS)"
+
diff --git a/lab3/build/xst.mk b/lab3/build/xst.mk
new file mode 100755
index 0000000..0610f14
--- /dev/null
+++ b/lab3/build/xst.mk
@@ -0,0 +1,130 @@
+# Command to initialize the Xilinx environment
+# (Feel free to change to the 64 bit version if necessary.)
+#XILINX_INIT = source /sw/xilinx/ise_11.1i/ISE/settings32.sh;
+#XILINX_INIT = source /extra/ise_11.1/ISE/settings32.sh;
+
+
+
+
+# This rule is responsible for creating the XST synthesis script and
+# the PRJ file containing the name of the files we want to synthesize
+
+.PRECIOUS: $(PROJNAME)-synthdir/%.scr $(PROJNAME)-synthdir/%.prj %.ncd $(PROJNAME)-synthdir/%.ngc $(PROJNAME)-synthdir/%.ngd $(PROJNAME)-synthdir/%_map.ncd $(PROJNAME)-synthdir/%.ncd $(PROJNAME)-synthdir/%.edf  %.ncd %.bit
+
+$(PROJNAME)-synthdir/xst/synth/design.scr: $(S)
+	@echo
+	@echo '*** Creating synthesis scripts ***'
+	@echo
+	mkdir -p $(@D)
+# We first create the project file
+	@rm -f $@.tmp
+	@echo "set -tmpdir tmpdir" > $@.tmp
+	@echo "run -ifn design.prj" >> $@.tmp
+	@echo "-ofn design.ngc" >> $@.tmp
+# The following lines finds the first specified synthesizable file,
+# removes the file extension by using sed and then removing the
+# directory part of the file by using basename. This is then used as
+# our top module!
+	echo "-top $$(basename $$(echo $(firstword $(S)) | sed 's/\..*$$//'))" >> $@.tmp
+	echo "-p $(PART)" >> $@.tmp
+	echo $(XST_OPT) >> $@.tmp
+# First enter all Verilog files into the project file, then all VHDL files
+	rm -f $(@D)/design.prj
+	touch $(@D)/design.prj
+	$(foreach i,$(filter %.v,$(S)), echo 'verilog work "$(call fixpath3,$(i))"' >> $(@D)/design.prj;)
+	$(foreach i,$(filter %.vhd,$(S)), echo 'vhdl work "$(call fixpath3,$(i))"' >> $(@D)/design.prj;)
+	$(foreach i,$(filter %.vhdl,$(S)), echo 'vhdl work "$(call fixpath3,$(i))"' >> $(@D)/design.prj;)
+	mv $@.tmp $@
+
+# Synthesize the design based on the synthesis script
+# Clean out temporary directories to be sure no stale data is left...
+$(PROJNAME)-synthdir/xst/synth/design.ngc: $(PROJNAME)-synthdir/xst/synth/design.scr 
+	@echo
+	@echo '*** Synthesizing ***'
+	@echo
+	rm -rf $(@D)/tmpdir
+	mkdir -p $(@D)/tmpdir
+	rm -rf $(@D)/xst
+	mkdir -p $(@D)/xst
+	cd $(@D); $(XILINX_INIT) xst -ifn design.scr -ofn design.syr
+
+POSTSYNTHSIMNETLIST=$(PROJNAME)-synthdir/xst/synth/design_postsynth.vhd
+
+$(POSTSYNTHSIMNETLIST): $(PROJNAME)-synthdir/xst/synth/design.ngc
+	@echo
+	@echo '*** Creating post synthesis netlist $* ***'
+	@echo
+	$(XILINX_INIT) netgen -w -ofmt vhdl $(@D)/design.ngc $@
+
+
+MODELSIM_POSTSYNTH_OPTIONS=-L unisim
+
+
+
+# TODO: Don't recompile all files all the time!
+PARSIM: work $(PROJNAME)-synthdir/layoutdefault/design_postpar.vhd SIMTBFILES
+	vcom +acc $(PROJNAME)-synthdir/layoutdefault/design_postpar.vhd
+	cp $(PROJNAME)-synthdir/layoutdefault/design_postpar.sdf .
+	vsim -sdfmax /uut=$(PROJNAME)-synthdir/layoutdefault/design_postpar.sdf -L simprim $$(basename $$(echo $(firstword $(T)) | sed 's/\..*$$//'))
+
+# TODO: Don't recompile all files all the time!
+PARSIMC: work $(PROJNAME)-synthdir/layoutdefault/design_postpar.vhd SIMTBFILES
+	vcom +acc $(PROJNAME)-synthdir/layoutdefault/design_postpar.vhd
+	vsim -sdfmax /uut=$(PROJNAME)-synthdir/layoutdefault/design_postpar.sdf -L simprim $$(basename $$(echo $(firstword $(T)) | sed 's/\..*$$//')) -c -do 'run -a; quit -f'
+
+
+# TODO: Don't recompile all files all the time!
+POWERSIM: work $(PROJNAME)-synthdir/layoutdefault/design_postpar.vhd SIMTBFILES
+	vcom +acc $(PROJNAME)-synthdir/layoutdefault/design_postpar.vhd
+	vsim -sdfmax /uut=$(PROJNAME)-synthdir/layoutdefault/design_postpar.sdf -do 'vcd file activity.vcd;vcd add -r -internal -in -out uut/*; vcd  on;run -a;vcd off;vcd flush;quit -f' -c -L simprim $$(basename $$(echo $(firstword $(T)) | sed 's/\..*$$//'))
+	$(XILINX_INIT) xpwr  -v -a -s activity.vcd   $(PROJNAME)-synthdir/layoutdefault/design.ncd 
+
+$(PROJNAME)-synthdir/synth/design.ngc: $(PROJNAME)-synthdir/xst/synth/design.ngc
+	mkdir -p $(@D)
+	cp $< $@
+
+export XST_EXTRA_OPTIONS
+
+
+
+dump_synthsettings:
+	@echo
+	@echo "   *** Important settings for the Synthesis module ***"
+	@echo
+	@echo "   Synthesis top module: $$(basename $$(echo $(firstword $(S)) | sed 's/\..*$$//'))"
+	@echo "   Files to synthesize:  $(S)"
+	@echo "   Include directories: $(INCDIRS)"
+	@echo "   FPGA part (PART): $(PART)"
+	@echo "   Extra options to XST: $(XST_EXTRA_OPTIONS) (FIXME - not implemented yet in Makefile!)"
+	@echo
+
+
+
+%.synth:  sanitychecksynth
+	$(NICE) $(MAKE) -f Makefile $*-synthdir/synth/design.ngc  PROJNAME="$*"
+
+
+
+
+
+
+%.synthsim:
+	$(NICE) $(MAKE) -f Makefile SYNTHSIM PROJNAME="$*" S="$(S)" U="$(U)" XST_OPT="$(XST_OPT)" PART="$(PART)" T="$(T)" INCDIRS="$(INCDIRS)"
+
+%.parsim:
+	$(NICE) $(MAKE) -f Makefile PARSIM PROJNAME="$*" S="$(S)" U="$(U)" XST_OPT="$(XST_OPT)" PART="$(PART)" T="$(T)" INCDIRS="$(INCDIRS)"
+
+
+
+%.parsimc:
+	$(NICE) $(MAKE) -f Makefile PARSIMC PROJNAME="$*" S="$(S)" U="$(U)" XST_OPT="$(XST_OPT)" PART="$(PART)" T="$(T)" INCDIRS="$(INCDIRS)"
+
+%.powersim:
+	$(NICE) $(MAKE) -f Makefile POWERSIM PROJNAME="$*" S="$(S)" U="$(U)" XST_OPT="$(XST_OPT)" PART="$(PART)" T="$(T)" INCDIRS="$(INCDIRS)"
+
+
+
+
+
+
+
diff --git a/lab3/lab.do b/lab3/lab.do
new file mode 100755
index 0000000..d9cfe5a
--- /dev/null
+++ b/lab3/lab.do
@@ -0,0 +1,38 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -divider lab_tb
+add wave -noupdate /lab_tb/clk
+add wave -noupdate /lab_tb/rst
+add wave -noupdate /lab_tb/rx
+add wave -noupdate /lab_tb/seg
+add wave -noupdate /lab_tb/an
+add wave -noupdate /lab_tb/tb_running
+add wave -noupdate /lab_tb/rxs
+add wave -noupdate -divider lab
+add wave -noupdate /lab_tb/uut/clk
+add wave -noupdate /lab_tb/uut/rst
+add wave -noupdate /lab_tb/uut/rx
+add wave -noupdate /lab_tb/uut/rx1
+add wave -noupdate /lab_tb/uut/rx2
+add wave -noupdate /lab_tb/uut/lp
+add wave -noupdate /lab_tb/uut/sp
+add wave -noupdate /lab_tb/uut/sreg
+add wave -noupdate -radix unsigned /lab_tb/uut/pos
+add wave -noupdate -radix hexadecimal /lab_tb/uut/tal
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {88676 ns} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits us
+update
+WaveRestoreZoom {0 ns} {525 us}
diff --git a/lab3/lab.ucf b/lab3/lab.ucf
new file mode 100755
index 0000000..2fc70ca
--- /dev/null
+++ b/lab3/lab.ucf
@@ -0,0 +1,37 @@
+#######################################################################
+# Define Device, Package, And Speed Grade
+#######################################################################
+#
+CONFIG PART = xc6slx16-3-csg324;
+
+#######################################################################
+# clk, rst
+#######################################################################
+##Clock signal
+Net "clk" LOC=V10 | IOSTANDARD=LVCMOS33;
+Net "clk" TNM_NET = sys_clk_pin;
+TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz;
+
+Net "rst" LOC = B8 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L33P, Sch name = BTNS
+
+######################################
+# Multiplexed display                #
+######################################
+## 7 segment display
+Net "seg<7>" LOC = M13 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L61N, Sch name = DP
+Net "seg<6>" LOC = T17 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L51P_M1DQ12, Sch name = CA
+Net "seg<5>" LOC = T18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L51N_M1DQ13, Sch name = CB
+Net "seg<4>" LOC = U17 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L52P_M1DQ14, Sch name = CC
+Net "seg<3>" LOC = U18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L52N_M1DQ15, Sch name = CD
+Net "seg<2>" LOC = M14 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L53P, Sch name = CE
+Net "seg<1>" LOC = N14 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L53N_VREF, Sch name = CF
+Net "seg<0>" LOC = L14 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L61P, Sch name = CG
+
+
+Net "an<0>" LOC = N16 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L50N_M1UDQSN, Sch name = AN0
+Net "an<1>" LOC = N15 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L50P_M1UDQS, Sch name = AN1
+Net "an<2>" LOC = P18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L49N_M1DQ11, Sch name = AN2
+Net "an<3>" LOC = P17 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L49P_M1DQ10, Sch name = AN3
+
+## Usb-RS232 interface
+Net "rx" LOC = N17 | IOSTANDARD=LVCMOS33; #Bank = 1, pin name = IO_L48P_HDC_M1DQ8, Sch name = MCU-RX
diff --git a/lab3/lab_tb.vhd b/lab3/lab_tb.vhd
new file mode 100755
index 0000000..17d032a
--- /dev/null
+++ b/lab3/lab_tb.vhd
@@ -0,0 +1,81 @@
+-- TestBench Template 
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY lab_tb IS
+END lab_tb;
+
+ARCHITECTURE behavior OF lab_tb IS 
+
+  -- Component Declaration
+  COMPONENT lab
+    PORT(
+      clk,rst,rx : IN std_logic;
+      seg: OUT unsigned(7 downto 0);       
+      an : OUT unsigned(3 downto 0)
+      );
+  END COMPONENT;
+
+  SIGNAL clk : std_logic := '0';
+  SIGNAL rst : std_logic := '0';
+  signal rx : std_logic := '1';
+  SIGNAL seg : unsigned(7 downto 0);
+  SIGNAL an :  unsigned(3 downto 0);
+  SIGNAL tb_running : boolean := true;
+  -- alla bitar för 1234
+  SIGNAL rxs :  unsigned(0 to 39) := "0100011001001001100101100110010001011001";
+BEGIN
+
+  -- Component Instantiation
+  uut: lab PORT MAP(
+    clk => clk,
+    rst => rst,
+    rx => rx,
+    seg => seg,
+    an => an);
+
+
+  clk_gen : process
+  begin
+    while tb_running loop
+      clk <= '0';
+      wait for 5 ns;
+      clk <= '1';
+      wait for 5 ns;
+    end loop;
+    wait;
+  end process;
+
+  
+
+  stimuli_generator : process
+    variable i : integer;
+  begin
+    -- Aktivera reset ett litet tag.
+    rst <= '1';
+    wait for 500 ns;
+
+    wait until rising_edge(clk);        -- se till att reset släpps synkront
+                                        -- med klockan
+    rst <= '0';
+    report "Reset released" severity note;
+    wait for 1 us;
+    
+    for i in 0 to 39 loop
+      rx <= rxs(i);
+      wait for 8.68 us;
+    end loop;  -- i
+    
+    for i in 0 to 50000000 loop         -- Vänta ett antal klockcykler
+      wait until rising_edge(clk);
+    end loop;  -- i
+    
+    tb_running <= false;                -- Stanna klockan (vilket medför att inga
+                                        -- nya event genereras vilket stannar
+                                        -- simuleringen).
+    wait;
+  end process;
+      
+END;
diff --git a/lab3/leddriver.vhd b/lab3/leddriver.vhd
new file mode 100755
index 0000000..f45a15c
--- /dev/null
+++ b/lab3/leddriver.vhd
@@ -0,0 +1,60 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.all;
+
+entity leddriver is
+    Port ( clk,rst : in  STD_LOGIC;
+           seg : out  UNSIGNED(7 downto 0);
+           an : out  UNSIGNED (3 downto 0);
+           value : in  UNSIGNED (15 downto 0));
+end leddriver;
+
+architecture Behavioral of leddriver is
+	signal segments : UNSIGNED (6 downto 0);
+	signal counter_r :  UNSIGNED(17 downto 0) := "000000000000000000";
+	signal v : UNSIGNED (3 downto 0);
+        signal dp : STD_LOGIC;
+begin
+  -- decimal point not used
+  dp <= '1';
+  seg <= (dp & segments);
+     
+   with counter_r(17 downto 16) select
+     v <= value(15 downto 12) when "00",
+          value(11 downto 8) when "01",	
+          value(7 downto 4) when "10",
+          value(3 downto 0) when others;
+
+   process(clk) begin
+     if rising_edge(clk) then 
+       counter_r <= counter_r + 1;
+       case v is
+         when "0000" => segments <= "0000001";
+         when "0001" => segments <= "1001111";
+         when "0010" => segments <= "0010010";
+         when "0011" => segments <= "0000110";
+         when "0100" => segments <= "1001100";
+         when "0101" => segments <= "0100100";
+         when "0110" => segments <= "0100000";
+         when "0111" => segments <= "0001111";
+         when "1000" => segments <= "0000000";
+         when "1001" => segments <= "0000100";
+         when "1010" => segments <= "0001000";
+         when "1011" => segments <= "1100000";
+         when "1100" => segments <= "0110001";
+         when "1101" => segments <= "1000010";
+         when "1110" => segments <= "0110000";
+         when others => segments <= "0111000";
+       end case;
+      
+       case counter_r(17 downto 16) is
+         when "00" => an <= "0111";
+         when "01" => an <= "1011";
+         when "10" => an <= "1101";
+         when others => an <= "1110";
+       end case;
+     end if;
+   end process;
+	
+end Behavioral;
+
diff --git a/lab3/sanitycheck b/lab3/sanitycheck
new file mode 100755
index 0000000..acdcc99
--- /dev/null
+++ b/lab3/sanitycheck
@@ -0,0 +1,21 @@
+#!/bin/bash
+
+if sed 's/--.*//' < "$1" | grep -n \'event
+then
+    echo "ERROR in $1: Du använder nyckelordet 'event. Om du vill kolla efter en klockflank bör rising_edge användas istället. Om du vill använda 'event till något annat i syntetiserbar kod bör du antagligen tänka om."
+    exit 1
+fi
+
+if sed 's/--.*//' < "$1" | egrep -n 'rising_edge *\(.*\)' | egrep -v 'rising_edge *\( *clk *\)'
+then
+    echo "ERROR in $1: Du försöker klocka på något som antagligen inte är en riktigt klocka. Du bör enbart använda rising_edge(clk) i din syntetiserbara kod."
+    exit 1
+fi
+
+if sed 's/--.*//' < "$1" | egrep -n 'falling_edge'
+then
+    echo "ERROR in $1: Du använder nyckelordet falling_edge i filen $1. I den här kursen bör du inte behöva använda det nyckelordet."
+    exit 1
+fi
+
+
diff --git a/lab3/sanitycheck.sh b/lab3/sanitycheck.sh
new file mode 100755
index 0000000..acdcc99
--- /dev/null
+++ b/lab3/sanitycheck.sh
@@ -0,0 +1,21 @@
+#!/bin/bash
+
+if sed 's/--.*//' < "$1" | grep -n \'event
+then
+    echo "ERROR in $1: Du använder nyckelordet 'event. Om du vill kolla efter en klockflank bör rising_edge användas istället. Om du vill använda 'event till något annat i syntetiserbar kod bör du antagligen tänka om."
+    exit 1
+fi
+
+if sed 's/--.*//' < "$1" | egrep -n 'rising_edge *\(.*\)' | egrep -v 'rising_edge *\( *clk *\)'
+then
+    echo "ERROR in $1: Du försöker klocka på något som antagligen inte är en riktigt klocka. Du bör enbart använda rising_edge(clk) i din syntetiserbara kod."
+    exit 1
+fi
+
+if sed 's/--.*//' < "$1" | egrep -n 'falling_edge'
+then
+    echo "ERROR in $1: Du använder nyckelordet falling_edge i filen $1. I den här kursen bör du inte behöva använda det nyckelordet."
+    exit 1
+fi
+
+
diff --git a/lab3/xst.mk b/lab3/xst.mk
new file mode 100755
index 0000000..4e4dc85
--- /dev/null
+++ b/lab3/xst.mk
@@ -0,0 +1,131 @@
+# Command to initialize the Xilinx environment
+# (Feel free to change to the 64 bit version if necessary.)
+#XILINX_INIT = source /sw/xilinx/ise_11.1i/ISE/settings32.sh;
+#XILINX_INIT = source /extra/ise_11.1/ISE/settings32.sh;
+
+
+
+
+# This rule is responsible for creating the XST synthesis script and
+# the PRJ file containing the name of the files we want to synthesize
+
+.PRECIOUS: $(PROJNAME)-synthdir/%.scr $(PROJNAME)-synthdir/%.prj %.ncd $(PROJNAME)-synthdir/%.ngc $(PROJNAME)-synthdir/%.ngd $(PROJNAME)-synthdir/%_map.ncd $(PROJNAME)-synthdir/%.ncd $(PROJNAME)-synthdir/%.edf  %.ncd %.bit
+
+$(PROJNAME)-synthdir/xst/synth/design.scr: $(S)
+	$(XILINX_INIT) xwebtalk -user off
+	@echo
+	@echo '*** Creating synthesis scripts ***'
+	@echo
+	mkdir -p $(@D)
+# We first create the project file
+	@rm -f $@.tmp
+	@echo "set -tmpdir tmpdir" > $@.tmp
+	@echo "run -ifn design.prj" >> $@.tmp
+	@echo "-ofn design.ngc" >> $@.tmp
+# The following lines finds the first specified synthesizable file,
+# removes the file extension by using sed and then removing the
+# directory part of the file by using basename. This is then used as
+# our top module!
+	echo "-top $$(basename $$(echo $(firstword $(S)) | sed 's/\..*$$//'))" >> $@.tmp
+	echo "-p $(PART)" >> $@.tmp
+	echo $(XST_OPT) >> $@.tmp
+# First enter all Verilog files into the project file, then all VHDL files
+	rm -f $(@D)/design.prj
+	touch $(@D)/design.prj
+	$(foreach i,$(filter %.v,$(S)), echo 'verilog work "$(call fixpath3,$(i))"' >> $(@D)/design.prj;)
+	$(foreach i,$(filter %.vhd,$(S)), echo 'vhdl work "$(call fixpath3,$(i))"' >> $(@D)/design.prj;)
+	$(foreach i,$(filter %.vhdl,$(S)), echo 'vhdl work "$(call fixpath3,$(i))"' >> $(@D)/design.prj;)
+	mv $@.tmp $@
+
+# Synthesize the design based on the synthesis script
+# Clean out temporary directories to be sure no stale data is left...
+$(PROJNAME)-synthdir/xst/synth/design.ngc: $(PROJNAME)-synthdir/xst/synth/design.scr 
+	@echo
+	@echo '*** Synthesizing ***'
+	@echo
+	rm -rf $(@D)/tmpdir
+	mkdir -p $(@D)/tmpdir
+	rm -rf $(@D)/xst
+	mkdir -p $(@D)/xst
+	cd $(@D); $(XILINX_INIT) xst -ifn design.scr -ofn design.syr
+
+POSTSYNTHSIMNETLIST=$(PROJNAME)-synthdir/xst/synth/design_postsynth.vhd
+
+$(POSTSYNTHSIMNETLIST): $(PROJNAME)-synthdir/xst/synth/design.ngc
+	@echo
+	@echo '*** Creating post synthesis netlist $* ***'
+	@echo
+	$(XILINX_INIT) netgen -w -ofmt vhdl $(@D)/design.ngc $@
+
+
+MODELSIM_POSTSYNTH_OPTIONS=-L unisim
+
+
+
+# TODO: Don't recompile all files all the time!
+PARSIM: work $(PROJNAME)-synthdir/layoutdefault/design_postpar.vhd SIMTBFILES
+	vcom +acc $(PROJNAME)-synthdir/layoutdefault/design_postpar.vhd
+	cp $(PROJNAME)-synthdir/layoutdefault/design_postpar.sdf .
+	vsim -sdfmax /uut=$(PROJNAME)-synthdir/layoutdefault/design_postpar.sdf -L simprim $$(basename $$(echo $(firstword $(T)) | sed 's/\..*$$//'))
+
+# TODO: Don't recompile all files all the time!
+PARSIMC: work $(PROJNAME)-synthdir/layoutdefault/design_postpar.vhd SIMTBFILES
+	vcom +acc $(PROJNAME)-synthdir/layoutdefault/design_postpar.vhd
+	vsim -sdfmax /uut=$(PROJNAME)-synthdir/layoutdefault/design_postpar.sdf -L simprim $$(basename $$(echo $(firstword $(T)) | sed 's/\..*$$//')) -c -do 'run -a; quit -f'
+
+
+# TODO: Don't recompile all files all the time!
+POWERSIM: work $(PROJNAME)-synthdir/layoutdefault/design_postpar.vhd SIMTBFILES
+	vcom +acc $(PROJNAME)-synthdir/layoutdefault/design_postpar.vhd
+	vsim -sdfmax /uut=$(PROJNAME)-synthdir/layoutdefault/design_postpar.sdf -do 'vcd file activity.vcd;vcd add -r -internal -in -out uut/*; vcd  on;run -a;vcd off;vcd flush;quit -f' -c -L simprim $$(basename $$(echo $(firstword $(T)) | sed 's/\..*$$//'))
+	$(XILINX_INIT) xpwr  -v -a -s activity.vcd   $(PROJNAME)-synthdir/layoutdefault/design.ncd 
+
+$(PROJNAME)-synthdir/synth/design.ngc: $(PROJNAME)-synthdir/xst/synth/design.ngc
+	mkdir -p $(@D)
+	cp $< $@
+
+export XST_EXTRA_OPTIONS
+
+
+
+dump_synthsettings:
+	@echo
+	@echo "   *** Important settings for the Synthesis module ***"
+	@echo
+	@echo "   Synthesis top module: $$(basename $$(echo $(firstword $(S)) | sed 's/\..*$$//'))"
+	@echo "   Files to synthesize:  $(S)"
+	@echo "   Include directories: $(INCDIRS)"
+	@echo "   FPGA part (PART): $(PART)"
+	@echo "   Extra options to XST: $(XST_EXTRA_OPTIONS) (FIXME - not implemented yet in Makefile!)"
+	@echo
+
+
+
+%.synth:  sanitychecksynth
+	$(NICE) $(MAKE) -f Makefile $*-synthdir/synth/design.ngc  PROJNAME="$*"
+
+
+
+
+
+
+%.synthsim:
+	$(NICE) $(MAKE) -f Makefile SYNTHSIM PROJNAME="$*" S="$(S)" U="$(U)" XST_OPT="$(XST_OPT)" PART="$(PART)" T="$(T)" INCDIRS="$(INCDIRS)"
+
+%.parsim:
+	$(NICE) $(MAKE) -f Makefile PARSIM PROJNAME="$*" S="$(S)" U="$(U)" XST_OPT="$(XST_OPT)" PART="$(PART)" T="$(T)" INCDIRS="$(INCDIRS)"
+
+
+
+%.parsimc:
+	$(NICE) $(MAKE) -f Makefile PARSIMC PROJNAME="$*" S="$(S)" U="$(U)" XST_OPT="$(XST_OPT)" PART="$(PART)" T="$(T)" INCDIRS="$(INCDIRS)"
+
+%.powersim:
+	$(NICE) $(MAKE) -f Makefile POWERSIM PROJNAME="$*" S="$(S)" U="$(U)" XST_OPT="$(XST_OPT)" PART="$(PART)" T="$(T)" INCDIRS="$(INCDIRS)"
+
+
+
+
+
+
+