woking and some suggestions from redovisning

1 files changed, 11 insertions, 18 deletions

diff --git a/lab3/lab.vhd b/lab3/lab.vhd
index d699e49..9489339 100755
--- a/lab3/lab.vhd
+++ b/lab3/lab.vhd
@@ -21,7 +21,7 @@ architecture Behavioral of lab is
                value : in  UNSIGNED (15 downto 0));
     end component;
 
-    signal sreg : UNSIGNED(9 downto 0) := B"0_00000000_0";  -- 10 bit skiftregister
+    signal sreg : UNSIGNED(9 downto 0) := B"0_0000_0000_0";  -- 10 bit skiftregister
     signal tal : UNSIGNED(15 downto 0) := X"0000";
     signal rx1,rx2 : std_logic;         -- vippor på insignalen
     signal sp : std_logic;              -- skiftpuls
@@ -83,7 +83,7 @@ begin
                     bit_cycle <= bit_cycle + 1;
                 end if;
             else -- not receiving
-                if rx2 = '0' and rx1 = '1' then
+                if rx2 = '0' then
                     -- received a start bit so start receiving
                     receiving <= '1';
                     bit_cycle <= X"1b2"; -- half, so we read in the middle
@@ -107,7 +107,7 @@ begin
                     sp <= '0';
                 end if;
                 if (sp = '1') and (receiving = '0') then
-                    lp <= '1'
+                    lp <= '1';
                 else
                     lp <= '0';
                 end if;
@@ -126,18 +126,11 @@ begin
     process(clk) begin
         if rising_edge(clk) then
             if rst = '1' then
-                sreg <= B"0_000_000_0";
+                sreg <= B"0_0000_0000_0";
             elsif sp = '1' then
-                sreg(0) <= sreg(1);
-                sreg(1) <= sreg(2);
-                sreg(2) <= sreg(3);
-                sreg(3) <= sreg(4);
-                sreg(4) <= sreg(5);
-                sreg(5) <= sreg(6);
-                sreg(6) <= sreg(7);
-                sreg(7) <= sreg(8);
-                sreg(8) <= sreg(9);
-                sreg(9) <= rx2;
+                sreg <= rx2 & sreg(9 downto 1);
+            elsif lp = '1' then
+                sreg <= B"0_0000_0000_0";
             end if;
         end if;
     end process;
@@ -177,13 +170,13 @@ begin
                 tal <= X"0000";
             elsif lp = '1' then
                 if pos = "00" then
-                    tal(3 downto 0) <= unsigned(sreg(8 downto 1));
+                    tal(3 downto 0) <= sreg(4 downto 1);
                 elsif pos = "01" then
-                    tal(7 downto 4) <= unsigned(sreg(8 downto 1));
+                    tal(7 downto 4) <= shift_right(sreg, 1)(3 downto 0);
                 elsif pos = "10" then
-                    tal(11 downto 8) <= unsigned(sreg(8 downto 1));
+                    tal(11 downto 8) <= shift_right(sreg, 1)(3 downto 0);
                 else
-                    tal(15 downto 12) <= unsigned(sreg(8 downto 1));
+                    tal(15 downto 12) <= shift_right(sreg, 1)(3 downto 0);
                 end if;
             end if;
         end if;