sporadic work

1 files changed, 62 insertions, 23 deletions

diff --git a/lab3/lab.vhd b/lab3/lab.vhd
index c8a1f3c..f50bfac 100755
--- a/lab3/lab.vhd
+++ b/lab3/lab.vhd
@@ -1,3 +1,7 @@
+-- slå på fpga
+-- stäng av modelsim
+-- make lab.prog
+
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.NUMERIC_STD.all;
@@ -24,6 +28,10 @@ architecture Behavioral of lab is
     signal lp : std_logic;              -- laddpuls
     signal pos : UNSIGNED(1 downto 0) := "00";
 
+    signal bit_cycle : UNSIGNED(11 downto 0) := X"000";  -- fits at least 868
+    signal bits_received : UNSIGNED(3 downto 0) := X"0";
+    signal receiving: std_logic; -- currently receiving a byte
+
 begin
     -- *****************************
     -- *  synkroniseringsvippor    *
@@ -56,11 +64,32 @@ begin
 
     process(clk) begin
         if rising_edge(clk) then
-            if rst='1' then
-                sp <= '0';
-                lp <= '0';
-            elsif _ then
-            else
+            if rst = '1' then
+                bit_cycle <= X"000";
+                bits_received <= X"0";
+                receiving <= '0';
+            elsif receiving = '1' then
+                -- have we waited for an uart cycle?
+                if bit_cycle = X"364" then
+                    -- yes. read uart data
+                    bits_received <= bits_received + 1;
+                    if bits_received = "10" then
+                        receiving <= '0';
+                    else
+                        bit_cycle <= X"000";
+                    end if;
+                else
+                    bit_cycle <= bit_cycle + 1;
+                end if;
+            else -- not receiving
+                if rx2 = '0' and rx1 = '1' then
+                    -- received a start bit so start receiving
+                    receiving <= '1';
+                    bit_cycle <= X"1b2"; -- half, so we read in the middle
+                    bits_received <= X"0";
+                else
+                    receiving <= '0';
+                end if;
             end if;
         end if;
     end process;
@@ -68,8 +97,13 @@ begin
     process(clk) begin
         if rising_edge(clk) then
             if rst='1' then
-            elsif _ then
+                lp <= '0';
+                sp <= '0';
             else
+                if (receiving = '1') and (bit_cycle = X"364") then
+                    sp <= '1';
+                    lp <= '1' if bits_received = "10" else '0';
+                end if;
             end if;
         end if;
     end process;
@@ -82,14 +116,14 @@ begin
     --
     -- De 10 bitarna i varje siffra skiftas in i skiftregistret.
 
-    process(clk) begin
-        if rising_edge(clk) then
-            if rst='1' then
-            elsif _ then
-            else
-            end if;
-        end if;
-    end process;
+    -- process(clk) begin
+    --     if rising_edge(clk) then
+    --         if rst='1' then
+    --         elsif _ then
+    --         else
+    --         end if;
+    --     end if;
+    -- end process;
 
 
     -- *****************************
@@ -100,7 +134,12 @@ begin
     process(clk) begin
         if rising_edge(clk) then
             if rst='1' then
-            elsif _ then
+            elsif lp = '1' then
+                if pos = "11" then
+                    pos <= "00";
+                else
+                    pos <= pos + 1;
+                end if;
             else
             end if;
         end if;
@@ -115,14 +154,14 @@ begin
     -- ... för 4 siffror. Laddas av laddpulsen, samtidigt räknas räknaren upp.
 
 
-    process(clk) begin
-        if rising_edge(clk) then
-            if rst='1' then
-            elsif _ then
-            else
-            end if;
-        end if;
-    end process;
+    -- process(clk) begin
+    --     if rising_edge(clk) then
+    --         if rst='1' then
+    --         elsif _ then
+    --         else
+    --         end if;
+    --     end if;
+    -- end process;
 
 
     -- *****************************