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| author | Gustav Sörnäs <gustav@sornas.net> | 2022-02-14 17:18:38 +0100 |
|---|---|---|
| committer | Gustav Sörnäs <gustav@sornas.net> | 2022-02-14 17:18:38 +0100 |
| commit | 82197955991947fe0872712460bb988b6c2d0ef9 (patch) | |
| tree | 3c91727a7ac088b197290fbf8486aba77ce8a9cf /lab3/lab_tb.vhd | |
| parent | 1ba036ef511af46a19fe81823b6e66bb4e98c45c (diff) | |
| download | tsea83-82197955991947fe0872712460bb988b6c2d0ef9.tar.gz | |
add rest of lab3
Diffstat (limited to 'lab3/lab_tb.vhd')
| -rwxr-xr-x | lab3/lab_tb.vhd | 81 |
1 files changed, 81 insertions, 0 deletions
diff --git a/lab3/lab_tb.vhd b/lab3/lab_tb.vhd new file mode 100755 index 0000000..17d032a --- /dev/null +++ b/lab3/lab_tb.vhd @@ -0,0 +1,81 @@ +-- TestBench Template + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY lab_tb IS +END lab_tb; + +ARCHITECTURE behavior OF lab_tb IS + + -- Component Declaration + COMPONENT lab + PORT( + clk,rst,rx : IN std_logic; + seg: OUT unsigned(7 downto 0); + an : OUT unsigned(3 downto 0) + ); + END COMPONENT; + + SIGNAL clk : std_logic := '0'; + SIGNAL rst : std_logic := '0'; + signal rx : std_logic := '1'; + SIGNAL seg : unsigned(7 downto 0); + SIGNAL an : unsigned(3 downto 0); + SIGNAL tb_running : boolean := true; + -- alla bitar för 1234 + SIGNAL rxs : unsigned(0 to 39) := "0100011001001001100101100110010001011001"; +BEGIN + + -- Component Instantiation + uut: lab PORT MAP( + clk => clk, + rst => rst, + rx => rx, + seg => seg, + an => an); + + + clk_gen : process + begin + while tb_running loop + clk <= '0'; + wait for 5 ns; + clk <= '1'; + wait for 5 ns; + end loop; + wait; + end process; + + + + stimuli_generator : process + variable i : integer; + begin + -- Aktivera reset ett litet tag. + rst <= '1'; + wait for 500 ns; + + wait until rising_edge(clk); -- se till att reset släpps synkront + -- med klockan + rst <= '0'; + report "Reset released" severity note; + wait for 1 us; + + for i in 0 to 39 loop + rx <= rxs(i); + wait for 8.68 us; + end loop; -- i + + for i in 0 to 50000000 loop -- Vänta ett antal klockcykler + wait until rising_edge(clk); + end loop; -- i + + tb_running <= false; -- Stanna klockan (vilket medför att inga + -- nya event genereras vilket stannar + -- simuleringen). + wait; + end process; + +END; |
