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| author | Gustav Sörnäs <gusso230@student.liu.se> | 2022-02-18 08:59:46 +0100 |
|---|---|---|
| committer | Gustav Sörnäs <gusso230@student.liu.se> | 2022-02-18 09:00:01 +0100 |
| commit | 22ee9c87ad40bf5f950284e959cf6af76de92306 (patch) | |
| tree | 7fc51240eeacb0743300e190e094feddaef836ea /lab4/VGA_lab.vhd | |
| parent | f14e713ff34532c9c7089c11e15b147f85d7580c (diff) | |
| download | tsea83-22ee9c87ad40bf5f950284e959cf6af76de92306.tar.gz | |
more align
Diffstat (limited to 'lab4/VGA_lab.vhd')
| -rw-r--r-- | lab4/VGA_lab.vhd | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/lab4/VGA_lab.vhd b/lab4/VGA_lab.vhd index 8d3c612..06e0c0c 100644 --- a/lab4/VGA_lab.vhd +++ b/lab4/VGA_lab.vhd @@ -53,7 +53,7 @@ architecture Behavioral of VGA_lab is data_out2 : out std_logic_vector(7 downto 0); -- data out addr2 : in unsigned(10 downto 0)); -- address end component; - + -- VGA motor component component VGA_MOTOR port ( clk : in std_logic; -- system clock @@ -66,16 +66,16 @@ architecture Behavioral of VGA_lab is Hsync : out std_logic; -- horizontal sync Vsync : out std_logic); -- vertical sync end component; - + -- intermediate signals between KBD_ENC and PICT_MEM signal data_s : std_logic_vector(7 downto 0); -- data signal addr_s : unsigned(10 downto 0); -- address signal we_s : std_logic; -- write enable - + -- intermediate signals between PICT_MEM and VGA_MOTOR signal data_out2_s : std_logic_vector(7 downto 0); -- data signal addr2_s : unsigned(10 downto 0); -- address - + begin -- keyboard encoder component connection |
