diff options
Diffstat (limited to 'lab4/VGA_MOTOR/VGA_MOTOR.vhd')
| -rw-r--r-- | lab4/VGA_MOTOR/VGA_MOTOR.vhd | 69 |
1 files changed, 48 insertions, 21 deletions
diff --git a/lab4/VGA_MOTOR/VGA_MOTOR.vhd b/lab4/VGA_MOTOR/VGA_MOTOR.vhd index dafe45d..6988ba8 100644 --- a/lab4/VGA_MOTOR/VGA_MOTOR.vhd +++ b/lab4/VGA_MOTOR/VGA_MOTOR.vhd @@ -13,31 +13,31 @@ use IEEE.NUMERIC_STD.ALL; -- IEEE library for the unsigned type -- entity
entity VGA_MOTOR is
- port ( clk : in std_logic;
- data : in std_logic_vector(7 downto 0);
- addr : out unsigned(10 downto 0);
- rst : in std_logic;
- vgaRed : out std_logic_vector(2 downto 0);
- vgaGreen : out std_logic_vector(2 downto 0);
- vgaBlue : out std_logic_vector(2 downto 1);
- Hsync : out std_logic;
- Vsync : out std_logic);
+ port ( clk : in std_logic; -- system clock
+ rst : in std_logic; -- reset
+ data : in std_logic_vector(7 downto 0); -- data
+ addr : out unsigned(10 downto 0); -- address
+ vgaRed : out std_logic_vector(2 downto 0); -- VGA red
+ vgaGreen : out std_logic_vector(2 downto 0); -- VGA green
+ vgaBlue : out std_logic_vector(2 downto 1); -- VGA blue
+ Hsync : out std_logic; -- horizontal sync
+ Vsync : out std_logic); -- vertical sync
end VGA_MOTOR;
-- architecture
architecture Behavioral of VGA_MOTOR is
- signal Xpixel : unsigned(9 downto 0); -- Horizontal pixel counter
- signal Ypixel : unsigned(9 downto 0); -- Vertical pixel counter
- signal ClkDiv : unsigned(1 downto 0); -- Clock divisor, to generate 25 MHz signal
- signal Clk25 : std_logic; -- One pulse width 25 MHz signal
-
- signal tilePixel : std_logic_vector(7 downto 0); -- Tile pixel data
+ signal Xpixel : unsigned(9 downto 0); -- Horizontal pixel counter
+ signal Ypixel : unsigned(9 downto 0); -- Vertical pixel counter
+ signal ClkDiv : unsigned(1 downto 0); -- Clock divisor, to generate 25 MHz signal
+ signal Clk25 : std_logic; -- One pulse width 25 MHz signal
+
+ signal tilePixel : std_logic_vector(7 downto 0); -- Tile pixel data
signal tileAddr : unsigned(10 downto 0); -- Tile address
signal blank : std_logic; -- blanking signal
-
+
-- Tile memory type
type ram_t is array (0 to 2047) of std_logic_vector(7 downto 0);
@@ -342,9 +342,9 @@ begin begin
if rising_edge(clk) then
if rst='1' then
- ClkDiv <= (others => '0');
+ ClkDiv <= (others => '0');
else
- ClkDiv <= ClkDiv + 1;
+ ClkDiv <= ClkDiv + 1;
end if;
end if;
end process;
@@ -361,8 +361,19 @@ begin -- * Xpixel *
-- * *
-- ***********************************
-
-
+ process(clk) begin
+ if rising_edge(clk) then
+ if rst = '1' then
+ Xpixel <= to_unsigned(0, 10);
+ elsif Clk25 = '1' then
+ if Xpixel = 800 then
+ Xpixel <= to_unsigned(0, 10);
+ else
+ Xpixel <= Xpixel + 1;
+ end if;
+ end if;
+ end if;
+ end process;
-- Horizontal sync
@@ -372,7 +383,7 @@ begin -- * Hsync *
-- * *
-- ***********************************
-
+ Hsync <= '1' when ((Xpixel > 656) and (Xpixel <= 752)) else '0';
-- Vertical pixel counter
@@ -383,6 +394,19 @@ begin -- * Ypixel *
-- * *
-- ***********************************
+ process(clk) begin
+ if rising_edge(clk) then
+ if rst = '1' then
+ Ypixel <= to_unsigned(0, 10);
+ elsif (Clk25 = '1') and (Xpixel = 800) then
+ if Ypixel = 521 then
+ Ypixel <= to_unsigned(0, 10);
+ else
+ Ypixel <= Ypixel + 1;
+ end if;
+ end if;
+ end if;
+ end process;
@@ -394,6 +418,7 @@ begin -- * Vsync *
-- * *
-- ***********************************
+ Vsync <= '1' when ((Ypixel > 490) and (Ypixel <= 492)) else '0';
@@ -406,6 +431,8 @@ begin -- * Blank *
-- * *
-- ***********************************
+
+ blank <= '0' when ((Xpixel <= 640) and (Ypixel <= 480)) else '1';
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