8 files changed, 577 insertions, 0 deletions
diff --git a/lab4/build/dc_synthesize.tcl b/lab4/build/dc_synthesize.tcl
new file mode 100644
index 0000000..45afc74
--- /dev/null
+++ b/lab4/build/dc_synthesize.tcl
@@ -0,0 +1,95 @@
+sh date
+
+# set some per design variables FIXME - use these!
+# set LOG_PATH  "synth/dc_test_synth/log/"
+# set GATE_PATH "synth/dc_test_synth/gate/"
+# set RTL_PATH  "synth/dc_test_synth/verilog/"
+
+# Should be moved to a synthesis setup dot file?
+set target_library {/sw/mentor/libraries/cmos065_522/CORE65LPLVT_5.1/libs/CORE65LPLVT_nom_1.20V_25C.db}
+set link_library $target_library 
+
+
+
+proc dir_exists {name} {
+    if { [catch {set type [file type $name] } ]  } {
+	return 0;
+    } 
+    if { $type == "directory" } {
+	return 1;
+    }
+    return 0;
+
+}
+
+source designinfo.tcl
+
+
+if {[dir_exists $TOPLEVEL.out]} {
+    sh rm -r ./$TOPLEVEL.out
+}
+sh mkdir ./$TOPLEVEL.out
+
+set power_preserve_rtl_hier_names true
+
+
+current_design $TOPLEVEL
+
+elaborate $TOPLEVEL
+
+# Set timing constaints, this says that a max of .5ns of delay from
+# input to output is allowable 
+#set_max_delay .1 -from [all_inputs] -to [all_outputs]
+
+
+# If this were a clocked piece of logic we could set a clock
+#  period to shoot for like this 
+set_clock_gating_style  -max_fanout 16
+
+# Some default settings, you probably need to change this for your
+# particular project!
+create_clock clk -period 2
+set_input_delay -clock clk 0.1 [all_inputs]
+set_output_delay -clock clk 0.1 [all_outputs]
+
+
+
+# FIXME - check this!
+#optimize_registers -sync_trans multiclass 
+
+# Check for warnings/errors 
+check_design
+
+# ungroup everything 
+ungroup -flatten -all
+
+# flatten it all, this forces all the hierarchy to be flattened out 
+set_flatten true -effort high
+uniquify
+
+# This forces the compiler to spend as much effort (and time)
+# compiling this RTL to achieve timing possible. 
+#
+# Clock gating is enabled by default to reduce power.
+compile_ultra -gate_clock
+
+# Now that the compile is complete report on the results 
+
+check_design > ./$TOPLEVEL.out/check_design.rpt
+
+report_constraint -all_violators -verbose  > constraint.rpt
+report_wire_load > wire_load_model_used.rpt
+report_area > area.rpt
+report_qor > qor.rpt
+report_timing -max_paths 1000 > timing.rpt
+
+
+report_ultra_optimization > ultraopt.rpt
+report_power -verbose > power_estimate.rpt
+report_design > ./$TOPLEVEL.out/design_information.rpt
+report_resources > ./$TOPLEVEL.out/resources.rpt
+
+# Finally write the post synthesis netlist out to a verilog file 
+write -f verilog -output synthesized_netlist.v -hierarchy
+
+quit
diff --git a/lab4/build/design_compiler.mk b/lab4/build/design_compiler.mk
new file mode 100644
index 0000000..35ed335
--- /dev/null
+++ b/lab4/build/design_compiler.mk
@@ -0,0 +1,30 @@
+
+$(PROJNAME)-synthdir/dc/synth/synth.tcl: build/dc_synthesize.tcl
+	@echo
+	@echo '*** Copying synthesis script ***'
+	@echo
+	mkdir -p $(@D)
+	cp build/dc_synthesize.tcl $(@D)/synth.tcl
+
+$(PROJNAME)-synthdir/dc/synth/designinfo.tcl: $(S)
+	@echo
+	@echo '*** Generate design info script ***'
+	@echo
+	mkdir -p $(@D)
+	rm -f $(@D)/designtmp
+	echo 'set TOPLEVEL '$$(basename $$(echo $(firstword $(S)) | sed 's/\..*$$//')) >> $@.tmp
+	$(foreach i,$(filter %.v,$(S)), echo 'read_verilog "$(call fixpath3,$(i))"' >> $@.tmp;)
+	$(foreach i,$(filter %.sv,$(S)), echo 'read_sverilog "$(call fixpath3,$(i))"' >> $@.tmp;)
+	$(foreach i,$(filter %.vhd,$(S)), echo 'read_vhdl "$(call fixpath3,$(i))"' >> $@.tmp;)
+	$(foreach i,$(filter %.vhdl,$(S)), echo 'read_vhdl "$(call fixpath3,$(i))"' >> $@.tmp;)
+	$(foreach i,$(filter %.v,$(S)), echo 'analyze -format verilog "$(call fixpath3,$(i))"' >> $@.tmp;)
+	$(foreach i,$(filter %.sv,$(S)), echo 'analyze -format sverilog "$(call fixpath3,$(i))"' >> $@.tmp;)
+	$(foreach i,$(filter %.vhd,$(S)), echo 'analyze -format vhdl "$(call fixpath3,$(i))"' >> $@.tmp;)
+	$(foreach i,$(filter %.vhdl,$(S)), echo 'analyze -format vhdl "$(call fixpath3,$(i))"' >> $@.tmp;)
+	mv $@.tmp $@
+
+$(PROJNAME)-synthdir/dc/synth/design.v: $(PROJNAME)-synthdir/dc/synth/synth.tcl $(PROJNAME)-synthdir/dc/synth/designinfo.tcl $(S)
+	cd $(PROJNAME)-synthdir/dc/synth; dc_shell -f synth.tcl
+
+%.synth: 
+	$(NICE) $(MAKE) -f $(firstword $(MAKEFILE_LIST)) $*-synthdir/dc/synth/design.v  PROJNAME="$*"
diff --git a/lab4/build/digilentprog.mk b/lab4/build/digilentprog.mk
new file mode 100644
index 0000000..8f55a5e
--- /dev/null
+++ b/lab4/build/digilentprog.mk
@@ -0,0 +1,6 @@
+
+PROG:
+	djtgcfg prog -i 0 -d Nexys3 -f $(PROJNAME)-synthdir/layoutdefault/design.bit
+
+%.prog:
+	$(NICE) $(MAKE) -f Makefile PROG PROJNAME="$*"
diff --git a/lab4/build/precision-xilinx.mk b/lab4/build/precision-xilinx.mk
new file mode 100644
index 0000000..fafa3bc
--- /dev/null
+++ b/lab4/build/precision-xilinx.mk
@@ -0,0 +1,59 @@
+PRECISION=precision
+
+# FIXME - different directoreis for different synthesis scripts?
+# For precision:
+$(PROJNAME)-synthdir/synth/precision/design.scr: $(S) | dump_synthsettings
+	@echo
+	@echo '*** Creating synthesis scripts for Precision ***'
+	@echo
+	mkdir -p $(@D)
+	rm -f $(@D)/design.scr;
+	echo set_results_dir . > $(@D)/design.scr
+	echo -n 'add_input_file {' >> $(@D)/design.scr
+	for i in $(S); do echo -n " \"$$PWD/$$i\"" >> $(@D)/design.scr; done
+	echo '}' >> $(@D)/design.scr
+	echo "setup_design -design "$$(basename $$(echo $(firstword $(S)) | sed 's/\..*$$//')) >> $(@D)/design.scr
+	echo 'setup_design -manufacturer $(PRECISION_MANUFACTURER) -family $(PRECISION_FAMILY)  -part $(PRECISION_PART) -speed $(PRECISION_SPEEDGRADE)' >> $(@D)/design.scr
+	echo '$(PRECISION_EXTRA_OPTIONS)'  >> $(@D)/design.scr
+	echo 'setup_design -basename design' >> $(@D)/design.scr
+	echo 'compile' >> $(@D)/design.scr
+	echo 'synthesize' >> $(@D)/design.scr
+	echo 'report_area > area.rpt' >> $(@D)/design.scr
+
+$(PROJNAME)-synthdir/synth/precision/design.edf: $(PROJNAME)-synthdir/synth/precision/design.scr
+	cd $(@D);$(NICE) $(PRECISION) -shell -file design.scr
+
+$(PROJNAME)-synthdir/synth/design.edf: $(PROJNAME)-synthdir/synth/precision/design.edf
+	cp $< $@
+
+dump_synthsettings:
+	@echo
+	@echo "   *** Important settings for the Synthesis module ***"
+	@echo
+	@echo "   Synthesis top module: $$(basename $$(echo $(firstword $(S)) | sed 's/\..*$$//'))"
+	@echo "   Files to synthesize:  $(S)"
+	@echo "   Include directories: $(INCDIRS)"
+	@echo "   FPGA part (PRECISION_PART): $(PRECISION_PART)"
+	@echo "   FPGA familypart (PRECISION_FAMILY): $(PRECISION_FAMILY)"
+	@echo "   FPGA manufacturer (PRECISION_MANUFACTURER): $(PRECISION_MANUFACTURER)"
+	@echo "   FPGA speedgrade (PRECISION_SPEEDGRADE): $(PRECISION_SPEEDGRADE)"
+	@echo "   Extra options to precision: $(PRECISION_EXTRA_OPTIONS)"
+	@echo
+
+export PRECISION_PART
+export PRECISION_FAMILY
+export PRECISION_MANUFACTURER
+export PRECISION_SPEEDGRADE
+export PRECISION_EXTRA_OPTIONS
+
+# How to handle EDN files?
+# $(PROJNAME)-synthdir/layoutdefault/design.ngd: $(PROJNAME)-synthdir/synth/design.ngc $(U)
+#     $(@D)/%.ngd: $(@D)/%.edf %.ucf
+#     	rm -rf $(@D)/_ngo
+#     	mkdir $(@D)/_ngo
+#     	cp *.edn $(@D)
+#     	cd $(@D); $(XILINX_INIT) ngdbuild -dd _ngo -nt timestamp -p $(PART) -uc $(PWD)/$*.ucf $*.edf  $*.ngd
+
+
+%.synth:
+	$(NICE) $(MAKE) -f $(firstword $(MAKEFILE_LIST)) $*-synthdir/synth/precision/design.edf  PROJNAME="$*"
diff --git a/lab4/build/util.mk b/lab4/build/util.mk
new file mode 100644
index 0000000..3bc84ca
--- /dev/null
+++ b/lab4/build/util.mk
@@ -0,0 +1,59 @@
+# Make sure we can include this from more than one place without any
+# issues:
+ifneq ($(UTILISINCLUDED),1)
+
+
+# The default shell for make is /bin/sh which doesn't work for some of
+# the commands used in these files.
+SHELL=/bin/bash
+
+
+# Make sure we are running at low priority...
+NICE = nice -n 19
+
+# Reverses the order of all arguments given to the function.
+reverse_order = $(if $(1), $(word $(words $(1)),$(1)) $(call reverse_order,$(wordlist 2,$(words $(1)),dummy $(1))),$(1))
+
+# Fix the path by inserting ../../.. if the path is relative. If absolute, do nothing
+fixpath3 = $(shell echo "$(1)" | sed 's,^\([^/]\),../../../\1,')
+
+# Fix the path by inserting ../.. if the path is relative. If absolute, do nothing
+fixpath2 = $(shell echo "$(1)" | sed 's,^\([^/]\),../../\1,')
+
+
+# Fix the path by inserting ../ if the path is relative. If absolute, do nothing
+fixpath1 = $(shell echo "$(1)" | sed 's,^\([^/]\),../\1,')
+
+export S
+export INCDIRS
+export T
+export U
+export PART
+export PROJNAME
+
+
+sanitycheckclock:
+	$(foreach i,$(S), bash sanitycheck.sh "$(i)" &&) true
+
+sanitychecksynth: sanitycheckclock
+	@if [ "$(S)" == "" ]; then echo 'ERROR: No synthesizable files specified!';false;fi
+
+sanitychecktb: sanitycheckclock
+	@if [ "$(T)" == "" ]; then echo 'ERROR: No testbench files specified!';false;fi
+	@if [ "$(S)" == "" ]; then echo 'WARNING: No synthesizable files specified!';fi
+
+
+
+%.clean:
+	rm -rf "$*-synthdir" "$*-simdir"
+
+
+
+clean:
+	rm -rf *synthdir *simdir *~
+
+
+
+UTILISINCLUDED=1
+endif
+
diff --git a/lab4/build/vsim.mk b/lab4/build/vsim.mk
new file mode 100644
index 0000000..a15219b
--- /dev/null
+++ b/lab4/build/vsim.mk
@@ -0,0 +1,61 @@
+# Needed for modelsim compilation of VHDL files
+T_REV=$(call reverse_order,$(T))
+S_REV=$(call reverse_order,$(S))
+
+#Enable this to set coverage...
+#COVERAGE=-cover bcst
+#FIXME - INCDIR handling
+
+VERILOGCOMPILE=vlog +acc $(COVERAGE) $(INCDIR)
+VHDLCOMPILE=vcom +acc $(COVERAGE)
+BATCHSIM?=vsim -c -do 'run -a;quit -f'
+GUISIM?=vsim
+
+# TODO: Don't recompile all files all the time!
+# (Re)compile all files used for the testbench
+
+$(PROJNAME)-simdir/work:
+	mkdir -p $(PROJNAME)-simdir
+	cd $(PROJNAME)-simdir;vlib work
+
+SIMTBFILES: $(PROJNAME)-simdir/work $(T_REV)
+	$(if $(filter %.vhd,$(T_REV)),  cd $(PROJNAME)-simdir; $(VHDLCOMPILE)	 $(foreach i, $(filter %.vhd, $(T_REV)), $(call fixpath1,$(i))))
+	$(if $(filter %.vhdl,$(T_REV)), cd $(PROJNAME)-simdir; $(VHDLCOMPILE)	 $(foreach i, $(filter %.vhdl, $(T_REV)), $(call fixpath1,$(i))))
+	$(if $(filter %.v,$(T_REV)),    cd $(PROJNAME)-simdir; $(VERILOGCOMPILE) $(foreach i, $(filter %.v, $(T_REV)), $(call fixpath1,$(i))))
+	$(if $(filter %.sv,$(T_REV)),   cd $(PROJNAME)-simdir; $(VERILOGCOMPILE) $(foreach i, $(filter %.sv, $(T_REV)), $(call fixpath1,$(i))))
+
+SIMSYNTHFILES: $(PROJNAME)-simdir/work $(S_REV)			
+	$(if $(filter %.vhd,$(S_REV)),  cd $(PROJNAME)-simdir; $(VHDLCOMPILE)	 $(foreach i, $(filter %.vhd, $(S_REV)), $(call fixpath1,$(i))))
+	$(if $(filter %.vhdl,$(S_REV)), cd $(PROJNAME)-simdir; $(VHDLCOMPILE)	 $(foreach i, $(filter %.vhdl, $(S_REV)), $(call fixpath1,$(i))))
+	$(if $(filter %.v,$(S_REV)),    cd $(PROJNAME)-simdir; $(VERILOGCOMPILE) $(foreach i, $(filter %.v, $(S_REV)), $(call fixpath1,$(i))))
+	$(if $(filter %.sv,$(S_REV)),   cd $(PROJNAME)-simdir; $(VERILOGCOMPILE) $(foreach i, $(filter %.sv, $(S_REV)), $(call fixpath1,$(i))))
+
+
+SIMFILES: SIMSYNTHFILES SIMTBFILES sanitychecktb sanitycheck
+
+# FIXME - How to handle for example  -L unisim ?
+SIM: SIMFILES
+	cd $(PROJNAME)-simdir;$(GUISIM) $$(basename $$(echo $(firstword $(T)) | sed 's/\..*$$//'))
+
+SIMC: SIMFILES
+	cd $(PROJNAME)-simdir; $(BATCHSIM) $$(basename $$(echo $(firstword $(T)) | sed 's/\..*$$//'))
+
+
+#	vcom  +acc $(PROJNAME)-synthdir/xst/synth//design_postsynth.vhd
+SYNTHSIMC: $(POSTSYNTHSIMNETLIST) SIMTBFILES
+	echo $*
+	$(NICE) $(MAKE) -f Makefile SIMC S="$(POSTSYNTHSIMNETLIST)" PROJNAME=$(PROJNAME) BATCHSIM="$(BATCHSIM) $(MODELSIM_POSTSYNTH_OPTIONS)"
+
+
+
+%.simfiles:
+	$(NICE) $(MAKE) -f Makefile SIMFILES PROJNAME="$*"
+
+%.sim:
+	$(NICE) $(MAKE) -f Makefile SIM PROJNAME="$*"
+
+%.simc:
+	$(NICE) $(MAKE) -f Makefile SIMC PROJNAME="$*"
+
+%.synthsimc:
+	$(NICE) $(MAKE) -f Makefile SYNTHSIMC PROJNAME="$*" 
diff --git a/lab4/build/xilinx-par.mk b/lab4/build/xilinx-par.mk
new file mode 100644
index 0000000..f178422
--- /dev/null
+++ b/lab4/build/xilinx-par.mk
@@ -0,0 +1,137 @@
+# FIXME - rule to create ngd file from edf file as well...
+
+dump_backendsettings:
+	@echo
+	@echo "   *** Important settings for the Xilinx Backend module ***"
+	@echo
+	@echo "   Synthesis top module: $$(basename $$(echo $(firstword $(S)) | sed 's/\..*$$//'))"
+	@echo "   FPGA part (PART): $(PART)"
+	@echo "   Constraints file: $(U)"
+	@echo
+
+
+# This is the default rule for NGDBuild when we are not trying to override our TIMESPEC
+$(PROJNAME)-synthdir/layoutdefault/%.ngd: $(PROJNAME)-synthdir/synth/design.ngc $(U) 
+	@echo
+	@echo '*** Producing NGD file ***'
+	@echo
+	rm -rf $(@D)/_ngo
+	mkdir -p $(@D)/_ngo
+# Running ngdbuild without any UCF file
+	if [ "$(U)" == "" ]; then \
+		cd $(@D); $(XILINX_INIT) ngdbuild -sd . -dd _ngo -nt timestamp -p $(PART) ../synth/design.ngc  design.ngd;\
+	else \
+		cd $(@D); $(XILINX_INIT) ngdbuild -sd . -dd _ngo -nt timestamp -p $(PART) -uc $(call fixpath2,$(U)) ../synth/design.ngc  design.ngd;\
+	fi
+
+
+# This is the default rule for NGDBuild when we are not trying to override our TIMESPEC
+$(PROJNAME)-synthdir/layoutdefault/%.ngd: $(PROJNAME)-synthdir/synth/design.edf $(U)
+	@echo
+	@echo '*** Producing NGD file ***'
+	@echo
+	rm -rf $(@D)/_ngo
+	mkdir -p $(@D)/_ngo
+# Running ngdbuild without any UCF file
+	if [ "$(U)" == "" ]; then \
+		cd $(@D); $(XILINX_INIT) ngdbuild -sd . -dd _ngo -nt timestamp -p $(PART) ../synth/design.edf  design.ngd;\
+	else \
+		cd $(@D); $(XILINX_INIT) ngdbuild -sd . -dd _ngo -nt timestamp -p $(PART) -uc $(call fixpath2,$(U)) ../synth/design.edf  design.ngd;\
+	fi
+
+
+# This is the rule for NGDBuild when we are trying to override the TIMESPEC when using a project.fmax rule
+$(PROJNAME)-synthdir/layout%/design.ngd: $(PROJNAME)-synthdir/synth/design.ngc $(U)
+	@echo
+	@echo '*** Producing NGD file ***'
+	@echo
+	rm -rf $(@D)/_ngo
+	mkdir -p $(@D)/_ngo
+	@if [ "$(U)" == "" ]; then \
+            echo 'Cannot synthesize to a specific MHz without a UCF file'; false; \
+        fi
+
+# At this point we try to override the default time constraint!
+	@if ! [ $$(grep -i TIMESPEC $(U) | wc -l) -eq 1 ]; then echo The script can only handle one timespec for now.;false;fi
+	@if ! egrep -q '^TIMESPEC ".*" *= *PERIOD *".*" *[0-9\.]+ *ns *HIGH *50 *% *;' $(U);then\
+            echo 'TIMESPEC line in UCF must be in the following format: TIMESPEC "name" = PERIOD 4.5 ns HIGH 50%;';\
+	    false;\
+        fi
+	sed 's/^\(TIMESPEC *".*" *= *PERIOD *".*"\) *[0-9\.]\+ *ns *HIGH  *50 *%; *$$/\1 $* HIGH 50%;/' < $(U) > $(@D)/design.ucf
+	@echo "*** UCF file setup for timespec $* ***"
+	cd $(@D); $(XILINX_INIT) ngdbuild -sd . -dd _ngo -nt timestamp -p $(PART) -uc design.ucf  ../synth/design.ngc  design.ngd
+
+
+
+# Map a design into the FPGA components
+$(PROJNAME)-synthdir/layout%/design_map.ncd $(PROJNAME)-synthdir/layout%/design.pcf: $(PROJNAME)-synthdir/layout%/design.ngd
+	@echo
+	@echo '*** Mapping design ***'
+	@echo
+	cd $(@D);$(XILINX_INIT) map -detail -u -p  $(PART) -pr b -c 100 -o design_map.ncd design.ngd design.pcf
+
+# Rule for placing and routing a design
+$(PROJNAME)-synthdir/layout%/design.ncd: $(PROJNAME)-synthdir/layout%/design_map.ncd $(PROJNAME)-synthdir/layout%/design.pcf
+	@echo
+	@echo '*** Routing design ***'
+	@echo
+	cd $(@D); $(XILINX_INIT) par -nopad -w  -ol high design_map.ncd design.ncd design.pcf 
+
+$(PROJNAME)-synthdir/layoutdefault/design_postpar.vhd: $(PROJNAME)-synthdir/layoutdefault/design.ncd
+	@echo
+	@echo '*** Creating post place and route netlist $* ***'
+	@echo
+	$(XILINX_INIT) netgen -w -ofmt vhdl $(@D)/design.ncd $@
+
+
+
+$(PROJNAME)-synthdir/layout%/design.twr: $(PROJNAME)-synthdir/layout%/design.ncd
+	@echo
+	@echo '*** Running static timing analysis ***'
+	@echo
+	cd $(@D); $(XILINX_INIT) trce -v 1000 design.ncd design.pcf
+
+$(PROJNAME)-synthdir/layoutdefault/design.xdl: work $(PROJNAME)-synthdir/layoutdefault/design.ncd
+	@echo
+	@echo '*** Creating XDL netlist ***'
+	@echo
+	cd $(@D); $(XILINX_INIT) xdl -w -ncd2xdl design.ncd
+
+
+$(PROJNAME)-synthdir/layoutdefault/design.bit: $(PROJNAME)-synthdir/layoutdefault/design.ncd
+	cd $(@D); $(XILINX_INIT) bitgen -w design.ncd
+
+
+# Duplicate the layout dependencies a couple of time with different
+# timespecs to enable parallel make to investigate several different
+# timing specs simultaneously on multi processor machines.
+#
+# Warning: You may have a limited amount of licenses for ISE!
+expandtimespec = $(shell echo 'scale=5;for(i=0;i<25;i+=1){$(1)-i*0.1;print " "}'|bc)
+$(PROJNAME)-synthdir/fmax.rpt: $(foreach i,$(call expandtimespec,$(TIMESPEC)),$(PROJNAME)-synthdir/layout$(i)/design.twr)
+	@echo 
+	@echo '*** Maximum frequencies follow ***'
+	@echo 
+	grep MHz $(PROJNAME)-synthdir/layout*/design.twr
+
+
+# The rules below are the only rules that are expected to actually be
+# called by a normal user of this makefile.
+
+%.bitgen: dump_backendsettings
+	$(NICE) $(MAKE) -f Makefile $*-synthdir/layoutdefault/design.bit PROJNAME="$*" S="$(S)" U="$(U)" XST_OPT="$(XST_OPT)" PART="$(PART)" INCDIRS="$(INCDIRS)"
+
+%.fmax: dump_backendsettings
+	$(NICE) $(MAKE) -f Makefile $*-synthdir/fmax.rpt  PROJNAME="$*" S="$(S)" U="$(U)" XST_OPT="$(XST_OPT)" PART="$(PART)" TIMESPEC=$(TIMESPEC) INCDIRS="$(INCDIRS)"
+
+
+
+%.route: dump_backendsettings
+	$(NICE) $(MAKE) -f Makefile $*-synthdir/layoutdefault/design.ncd  PROJNAME="$*" S="$(S)" U="$(U)" XST_OPT="$(XST_OPT)" PART="$(PART)" INCDIRS="$(INCDIRS)"
+
+%.timing: dump_backendsettings
+	$(NICE) $(MAKE) -f Makefile $*-synthdir/layoutdefault/design.twr PROJNAME="$*" S="$(S)" U="$(U)" XST_OPT="$(XST_OPT)" PART="$(PART)" INCDIRS="$(INCDIRS)"
+
+%.xdl: dump_backendsettings
+	$(NICE) $(MAKE) -f Makefile $*-synthdir/layoutdefault/design.xdl PROJNAME="$*" S="$(S)" U="$(U)" XST_OPT="$(XST_OPT)" PART="$(PART)" T="$(T)" INCDIRS="$(INCDIRS)"
+
diff --git a/lab4/build/xst.mk b/lab4/build/xst.mk
new file mode 100644
index 0000000..0610f14
--- /dev/null
+++ b/lab4/build/xst.mk
@@ -0,0 +1,130 @@
+# Command to initialize the Xilinx environment
+# (Feel free to change to the 64 bit version if necessary.)
+#XILINX_INIT = source /sw/xilinx/ise_11.1i/ISE/settings32.sh;
+#XILINX_INIT = source /extra/ise_11.1/ISE/settings32.sh;
+
+
+
+
+# This rule is responsible for creating the XST synthesis script and
+# the PRJ file containing the name of the files we want to synthesize
+
+.PRECIOUS: $(PROJNAME)-synthdir/%.scr $(PROJNAME)-synthdir/%.prj %.ncd $(PROJNAME)-synthdir/%.ngc $(PROJNAME)-synthdir/%.ngd $(PROJNAME)-synthdir/%_map.ncd $(PROJNAME)-synthdir/%.ncd $(PROJNAME)-synthdir/%.edf  %.ncd %.bit
+
+$(PROJNAME)-synthdir/xst/synth/design.scr: $(S)
+	@echo
+	@echo '*** Creating synthesis scripts ***'
+	@echo
+	mkdir -p $(@D)
+# We first create the project file
+	@rm -f $@.tmp
+	@echo "set -tmpdir tmpdir" > $@.tmp
+	@echo "run -ifn design.prj" >> $@.tmp
+	@echo "-ofn design.ngc" >> $@.tmp
+# The following lines finds the first specified synthesizable file,
+# removes the file extension by using sed and then removing the
+# directory part of the file by using basename. This is then used as
+# our top module!
+	echo "-top $$(basename $$(echo $(firstword $(S)) | sed 's/\..*$$//'))" >> $@.tmp
+	echo "-p $(PART)" >> $@.tmp
+	echo $(XST_OPT) >> $@.tmp
+# First enter all Verilog files into the project file, then all VHDL files
+	rm -f $(@D)/design.prj
+	touch $(@D)/design.prj
+	$(foreach i,$(filter %.v,$(S)), echo 'verilog work "$(call fixpath3,$(i))"' >> $(@D)/design.prj;)
+	$(foreach i,$(filter %.vhd,$(S)), echo 'vhdl work "$(call fixpath3,$(i))"' >> $(@D)/design.prj;)
+	$(foreach i,$(filter %.vhdl,$(S)), echo 'vhdl work "$(call fixpath3,$(i))"' >> $(@D)/design.prj;)
+	mv $@.tmp $@
+
+# Synthesize the design based on the synthesis script
+# Clean out temporary directories to be sure no stale data is left...
+$(PROJNAME)-synthdir/xst/synth/design.ngc: $(PROJNAME)-synthdir/xst/synth/design.scr 
+	@echo
+	@echo '*** Synthesizing ***'
+	@echo
+	rm -rf $(@D)/tmpdir
+	mkdir -p $(@D)/tmpdir
+	rm -rf $(@D)/xst
+	mkdir -p $(@D)/xst
+	cd $(@D); $(XILINX_INIT) xst -ifn design.scr -ofn design.syr
+
+POSTSYNTHSIMNETLIST=$(PROJNAME)-synthdir/xst/synth/design_postsynth.vhd
+
+$(POSTSYNTHSIMNETLIST): $(PROJNAME)-synthdir/xst/synth/design.ngc
+	@echo
+	@echo '*** Creating post synthesis netlist $* ***'
+	@echo
+	$(XILINX_INIT) netgen -w -ofmt vhdl $(@D)/design.ngc $@
+
+
+MODELSIM_POSTSYNTH_OPTIONS=-L unisim
+
+
+
+# TODO: Don't recompile all files all the time!
+PARSIM: work $(PROJNAME)-synthdir/layoutdefault/design_postpar.vhd SIMTBFILES
+	vcom +acc $(PROJNAME)-synthdir/layoutdefault/design_postpar.vhd
+	cp $(PROJNAME)-synthdir/layoutdefault/design_postpar.sdf .
+	vsim -sdfmax /uut=$(PROJNAME)-synthdir/layoutdefault/design_postpar.sdf -L simprim $$(basename $$(echo $(firstword $(T)) | sed 's/\..*$$//'))
+
+# TODO: Don't recompile all files all the time!
+PARSIMC: work $(PROJNAME)-synthdir/layoutdefault/design_postpar.vhd SIMTBFILES
+	vcom +acc $(PROJNAME)-synthdir/layoutdefault/design_postpar.vhd
+	vsim -sdfmax /uut=$(PROJNAME)-synthdir/layoutdefault/design_postpar.sdf -L simprim $$(basename $$(echo $(firstword $(T)) | sed 's/\..*$$//')) -c -do 'run -a; quit -f'
+
+
+# TODO: Don't recompile all files all the time!
+POWERSIM: work $(PROJNAME)-synthdir/layoutdefault/design_postpar.vhd SIMTBFILES
+	vcom +acc $(PROJNAME)-synthdir/layoutdefault/design_postpar.vhd
+	vsim -sdfmax /uut=$(PROJNAME)-synthdir/layoutdefault/design_postpar.sdf -do 'vcd file activity.vcd;vcd add -r -internal -in -out uut/*; vcd  on;run -a;vcd off;vcd flush;quit -f' -c -L simprim $$(basename $$(echo $(firstword $(T)) | sed 's/\..*$$//'))
+	$(XILINX_INIT) xpwr  -v -a -s activity.vcd   $(PROJNAME)-synthdir/layoutdefault/design.ncd 
+
+$(PROJNAME)-synthdir/synth/design.ngc: $(PROJNAME)-synthdir/xst/synth/design.ngc
+	mkdir -p $(@D)
+	cp $< $@
+
+export XST_EXTRA_OPTIONS
+
+
+
+dump_synthsettings:
+	@echo
+	@echo "   *** Important settings for the Synthesis module ***"
+	@echo
+	@echo "   Synthesis top module: $$(basename $$(echo $(firstword $(S)) | sed 's/\..*$$//'))"
+	@echo "   Files to synthesize:  $(S)"
+	@echo "   Include directories: $(INCDIRS)"
+	@echo "   FPGA part (PART): $(PART)"
+	@echo "   Extra options to XST: $(XST_EXTRA_OPTIONS) (FIXME - not implemented yet in Makefile!)"
+	@echo
+
+
+
+%.synth:  sanitychecksynth
+	$(NICE) $(MAKE) -f Makefile $*-synthdir/synth/design.ngc  PROJNAME="$*"
+
+
+
+
+
+
+%.synthsim:
+	$(NICE) $(MAKE) -f Makefile SYNTHSIM PROJNAME="$*" S="$(S)" U="$(U)" XST_OPT="$(XST_OPT)" PART="$(PART)" T="$(T)" INCDIRS="$(INCDIRS)"
+
+%.parsim:
+	$(NICE) $(MAKE) -f Makefile PARSIM PROJNAME="$*" S="$(S)" U="$(U)" XST_OPT="$(XST_OPT)" PART="$(PART)" T="$(T)" INCDIRS="$(INCDIRS)"
+
+
+
+%.parsimc:
+	$(NICE) $(MAKE) -f Makefile PARSIMC PROJNAME="$*" S="$(S)" U="$(U)" XST_OPT="$(XST_OPT)" PART="$(PART)" T="$(T)" INCDIRS="$(INCDIRS)"
+
+%.powersim:
+	$(NICE) $(MAKE) -f Makefile POWERSIM PROJNAME="$*" S="$(S)" U="$(U)" XST_OPT="$(XST_OPT)" PART="$(PART)" T="$(T)" INCDIRS="$(INCDIRS)"
+
+
+
+
+
+
+