From 1ba036ef511af46a19fe81823b6e66bb4e98c45c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Gustav=20S=C3=B6rn=C3=A4s?= <gustav@sornas.net>
Date: Mon, 14 Feb 2022 17:17:31 +0100
Subject: add lab3 vhdl template

---
 lab3/lab.vhd | 72 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 72 insertions(+)
 create mode 100755 lab3/lab.vhd

(limited to 'lab3/lab.vhd')

diff --git a/lab3/lab.vhd b/lab3/lab.vhd
new file mode 100755
index 0000000..22bf366
--- /dev/null
+++ b/lab3/lab.vhd
@@ -0,0 +1,72 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.all;
+
+
+entity lab is
+    Port ( clk,rst, rx : in  STD_LOGIC;    -- rst är tryckknappen i mitten under displayen
+           seg: out  UNSIGNED(7 downto 0);
+           an : out  UNSIGNED (3 downto 0));
+end lab;
+
+architecture Behavioral of lab is
+
+  component leddriver
+    Port ( clk,rst : in  STD_LOGIC;
+           seg : out  UNSIGNED(7 downto 0);
+           an : out  UNSIGNED (3 downto 0);
+           value : in  UNSIGNED (15 downto 0));
+  end component;
+
+    signal sreg : UNSIGNED(9 downto 0) := B"0_00000000_0";  -- 10 bit skiftregister
+    signal tal : UNSIGNED(15 downto 0) := X"0000";
+    signal rx1,rx2 : std_logic;         -- vippor på insignalen
+    signal sp : std_logic;              -- skiftpuls
+    signal lp : std_logic;              -- laddpuls
+    signal pos : UNSIGNED(1 downto 0) := "00";
+
+begin
+
+    process(clk) begin
+        if rising_edge(clk) then
+            if rst='1' then
+                -- init
+            elsif false then
+                -- do the thing
+            else
+                -- do the other thing
+            end if;
+        end if;
+    end process;
+
+  -- *****************************
+  -- *  synkroniseringsvippor    *
+  -- *****************************
+
+  -- *****************************
+  -- *       styrenhet           *
+  -- *****************************
+
+
+  -- *****************************
+  -- * 10 bit skiftregister      *
+  -- *****************************
+
+
+  -- *****************************
+  -- * 2  bit register           *
+  -- *****************************
+
+
+  -- *****************************
+  -- * 16 bit register           *
+  -- *****************************
+
+
+  -- *****************************
+  -- * Multiplexad display       *
+  -- *****************************
+  -- Inkoppling av komponenten leddriver
+  led: leddriver port map (clk, rst, seg, an, tal);
+
+end Behavioral;
-- 
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