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-- slå på fpga
-- stäng av modelsim
-- make lab.prog
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;
entity lab is
Port ( clk, rst, rx : in STD_LOGIC; -- rst är tryckknappen i mitten under displayen
seg: out UNSIGNED(7 downto 0);
an : out UNSIGNED (3 downto 0));
end lab;
architecture Behavioral of lab is
component leddriver
Port ( clk,rst : in STD_LOGIC;
seg : out UNSIGNED(7 downto 0);
an : out UNSIGNED (3 downto 0);
value : in UNSIGNED (15 downto 0));
end component;
signal sreg : UNSIGNED(9 downto 0) := B"0_00000000_0"; -- 10 bit skiftregister
signal tal : UNSIGNED(15 downto 0) := X"0000";
signal rx1,rx2 : std_logic; -- vippor på insignalen
signal sp : std_logic; -- skiftpuls
signal lp : std_logic; -- laddpuls
signal pos : UNSIGNED(1 downto 0) := "00";
signal bit_cycle : UNSIGNED(11 downto 0) := X"000"; -- fits at least 868
signal bits_received : UNSIGNED(3 downto 0) := X"0";
signal receiving: std_logic; -- currently receiving a byte
begin
-- *****************************
-- * synkroniseringsvippor *
-- *****************************
-- 1 process
--
-- Förändringarna på insignalen ska komma i takt med vår klocka.
process(clk) begin
if rising_edge(clk) then
if rst='1' then
rx1 <= '0';
rx2 <= '0';
else
rx1 <= rx;
rx2 <= rx1;
end if;
end if;
end process;
-- *****************************
-- * styrenhet *
-- *****************************
-- 1 eller 2 processer
--
-- Denna producerar två styrsignaler, båda enpulsade:
-- – Skiftpulsen sp, som kommer mitt i (ungefär) varje bit.
-- – Laddpulsen lp, som kommer efter den sista skiftpulsen.
process(clk) begin
if rising_edge(clk) then
if rst = '1' then
bit_cycle <= X"000";
bits_received <= X"0";
receiving <= '0';
elsif receiving = '1' then
-- have we waited for an uart cycle?
if bit_cycle = X"364" then
-- yes. read uart data
bits_received <= bits_received + 1;
if bits_received = "10" then
receiving <= '0';
else
bit_cycle <= X"000";
end if;
else
bit_cycle <= bit_cycle + 1;
end if;
else -- not receiving
if rx2 = '0' and rx1 = '1' then
-- received a start bit so start receiving
receiving <= '1';
bit_cycle <= X"1b2"; -- half, so we read in the middle
bits_received <= X"0";
else
receiving <= '0';
end if;
end if;
end if;
end process;
process(clk) begin
if rising_edge(clk) then
if rst='1' then
lp <= '0';
sp <= '0';
else
if (receiving = '1') and (bit_cycle = X"364") then
sp <= '1';
lp <= '1' if bits_received = "10" else '0';
end if;
end if;
end if;
end process;
-- *****************************
-- * 10 bit skiftregister *
-- *****************************
-- 1 process
--
-- De 10 bitarna i varje siffra skiftas in i skiftregistret.
-- process(clk) begin
-- if rising_edge(clk) then
-- if rst='1' then
-- elsif _ then
-- else
-- end if;
-- end if;
-- end process;
-- *****************************
-- * 2 bit räknare *
-- *****************************
-- 1 process
process(clk) begin
if rising_edge(clk) then
if rst='1' then
elsif lp = '1' then
if pos = "11" then
pos <= "00";
else
pos <= pos + 1;
end if;
else
end if;
end if;
end process;
-- *****************************
-- * 16 bit register *
-- *****************************
-- 1 process
--
-- ... för 4 siffror. Laddas av laddpulsen, samtidigt räknas räknaren upp.
-- process(clk) begin
-- if rising_edge(clk) then
-- if rst='1' then
-- elsif _ then
-- else
-- end if;
-- end if;
-- end process;
-- *****************************
-- * Multiplexad display *
-- *****************************
-- Inkoppling av komponenten leddriver
led: leddriver port map (clk, rst, seg, an, tal);
end Behavioral;
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